1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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116 DynInstPtr insts[Impl::MaxWidth];
117};
118
119/** Struct that defines all backwards communication. */
120template<class Impl>
121struct TimeBufStruct {
122 typedef typename Impl::DynInstPtr DynInstPtr;
123 struct decodeComm {
124 uint64_t branchAddr;
125 InstSeqNum doneSeqNum;
126 DynInstPtr mispredictInst;
127 DynInstPtr squashInst;
128 Addr mispredPC;
129 TheISA::PCState nextPC;
130 unsigned branchCount;
131 bool squash;
132 bool predIncorrect;
133 bool branchMispredict;
134 bool branchTaken;
135 };
136
137 decodeComm decodeInfo[Impl::MaxThreads];
138
139 struct renameComm {
140 };
141
142 renameComm renameInfo[Impl::MaxThreads];
143
144 struct iewComm {
145 // Also eventually include skid buffer space.
146 bool usedIQ;
147 unsigned freeIQEntries;
148 bool usedLSQ;
149 unsigned freeLSQEntries;
150
151 unsigned iqCount;
152 unsigned ldstqCount;
153
154 unsigned dispatched;
155 unsigned dispatchedToLSQ;
156 };
157
158 iewComm iewInfo[Impl::MaxThreads];
159
160 struct commitComm {
161
162 /////////////// For Decode, IEW, Rename, Fetch ///////////
163 bool squash;
164 bool robSquashing;
165
166 ////////// For Fetch & IEW /////////////
167 // Represents the instruction that has either been retired or
168 // squashed. Similar to having a single bus that broadcasts the
169 // retired or squashed sequence number.
170 InstSeqNum doneSeqNum;
171
172 ////////////// For Rename /////////////////
173 // Rename should re-read number of free rob entries
174 bool usedROB;
175 // Notify Rename that the ROB is empty
176 bool emptyROB;
177 // Tell Rename how many free entries it has in the ROB
178 unsigned freeROBEntries;
179
180
181 ///////////// For Fetch //////////////////
182 // Provide fetch the instruction that mispredicted, if this
183 // pointer is not-null a misprediction occured
184 DynInstPtr mispredictInst;
185 // Was the branch taken or not
186 bool branchTaken;
187 // The pc of the next instruction to execute. This is the next
188 // instruction for a branch mispredict, but the same instruction for
189 // order violation and the like
190 TheISA::PCState pc;
191
192 // Instruction that caused the a non-mispredict squash
193 DynInstPtr squashInst;
194 // If an interrupt is pending and fetch should stall
195 bool interruptPending;
196 // If the interrupt ended up being cleared before being handled
197 bool clearInterrupt;
198
199 //////////// For IEW //////////////////
200 // Communication specifically to the IQ to tell the IQ that it can
201 // schedule a non-speculative instruction.
202 InstSeqNum nonSpecSeqNum;
203
204 // Hack for now to send back an uncached access to the IEW stage.
205 bool uncached;
206 DynInstPtr uncachedLoad;
207
208 };
209
210 commitComm commitInfo[Impl::MaxThreads];
211
212 bool decodeBlock[Impl::MaxThreads];
213 bool decodeUnblock[Impl::MaxThreads];
214 bool renameBlock[Impl::MaxThreads];
215 bool renameUnblock[Impl::MaxThreads];
216 bool iewBlock[Impl::MaxThreads];
217 bool iewUnblock[Impl::MaxThreads];
218 bool commitBlock[Impl::MaxThreads];
219 bool commitUnblock[Impl::MaxThreads];
220};
221
222#endif //__CPU_O3_COMM_HH__