1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_COMM_HH__
44#define __CPU_O3_COMM_HH__
45
46#include <vector>
47
48#include "arch/types.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "sim/faults.hh"
52
53// Typedef for physical register index type. Although the Impl would be the
54// most likely location for this, there are a few classes that need this
55// typedef yet are not templated on the Impl. For now it will be defined here.
56typedef short int PhysRegIndex;
57
58/** Struct that defines the information passed from fetch to decode. */
59template<class Impl>
60struct DefaultFetchDefaultDecode {
61 typedef typename Impl::DynInstPtr DynInstPtr;
62
63 int size;
64
65 DynInstPtr insts[Impl::MaxWidth];
66 Fault fetchFault;
67 InstSeqNum fetchFaultSN;
68 bool clearFetchFault;
69};
70
71/** Struct that defines the information passed from decode to rename. */
72template<class Impl>
73struct DefaultDecodeDefaultRename {
74 typedef typename Impl::DynInstPtr DynInstPtr;
75
76 int size;
77
78 DynInstPtr insts[Impl::MaxWidth];
79};
80
81/** Struct that defines the information passed from rename to IEW. */
82template<class Impl>
83struct DefaultRenameDefaultIEW {
84 typedef typename Impl::DynInstPtr DynInstPtr;
85
86 int size;
87
88 DynInstPtr insts[Impl::MaxWidth];
89};
90
91/** Struct that defines the information passed from IEW to commit. */
92template<class Impl>
93struct DefaultIEWDefaultCommit {
94 typedef typename Impl::DynInstPtr DynInstPtr;
95
96 int size;
97
98 DynInstPtr insts[Impl::MaxWidth];
99
100 bool squash[Impl::MaxThreads];
101 bool branchMispredict[Impl::MaxThreads];
102 DynInstPtr mispredictInst[Impl::MaxThreads];
103 bool branchTaken[Impl::MaxThreads];
104 Addr mispredPC[Impl::MaxThreads];
105 TheISA::PCState pc[Impl::MaxThreads];
106 InstSeqNum squashedSeqNum[Impl::MaxThreads];
107
108 bool includeSquashInst[Impl::MaxThreads];
109};
110
111template<class Impl>
112struct IssueStruct {
113 typedef typename Impl::DynInstPtr DynInstPtr;
114
115 int size;
116
117 DynInstPtr insts[Impl::MaxWidth];
118};
119
120/** Struct that defines all backwards communication. */
121template<class Impl>
122struct TimeBufStruct {
123 typedef typename Impl::DynInstPtr DynInstPtr;
124 struct decodeComm {
125 bool squash;
126 bool predIncorrect;
127 uint64_t branchAddr;
128
129 InstSeqNum doneSeqNum;
130
131 // @todo: Might want to package this kind of branch stuff into a single
132 // struct as it is used pretty frequently.
133 bool branchMispredict;
134 DynInstPtr mispredictInst;
135 bool branchTaken;
136 Addr mispredPC;
137 TheISA::PCState nextPC;
138 unsigned branchCount;
139 };
140
141 decodeComm decodeInfo[Impl::MaxThreads];
142
143 struct renameComm {
144 };
145
146 renameComm renameInfo[Impl::MaxThreads];
147
148 struct iewComm {
149 // Also eventually include skid buffer space.
150 bool usedIQ;
151 unsigned freeIQEntries;
152 bool usedLSQ;
153 unsigned freeLSQEntries;
154
155 unsigned iqCount;
156 unsigned ldstqCount;
157
158 unsigned dispatched;
159 unsigned dispatchedToLSQ;
160 };
161
162 iewComm iewInfo[Impl::MaxThreads];
163
164 struct commitComm {
165
166 /////////////// For Decode, IEW, Rename, Fetch ///////////
167 bool squash;
168 bool robSquashing;
169
170 ////////// For Fetch & IEW /////////////
171 // Represents the instruction that has either been retired or
172 // squashed. Similar to having a single bus that broadcasts the
173 // retired or squashed sequence number.
174 InstSeqNum doneSeqNum;
175
176 ////////////// For Rename /////////////////
177 // Rename should re-read number of free rob entries
178 bool usedROB;
179 // Notify Rename that the ROB is empty
180 bool emptyROB;
181 // Tell Rename how many free entries it has in the ROB
182 unsigned freeROBEntries;
183
184
185 ///////////// For Fetch //////////////////
186 // Provide fetch the instruction that mispredicted, if this
187 // pointer is not-null a misprediction occured
188 DynInstPtr mispredictInst;
189 // Was the branch taken or not
190 bool branchTaken;
191 // The pc of the next instruction to execute. This is the next
192 // instruction for a branch mispredict, but the same instruction for
193 // order violation and the like
194 TheISA::PCState pc;
195
196 // Instruction that caused the a non-mispredict squash
197 DynInstPtr squashInst;
198 // If an interrupt is pending and fetch should stall
199 bool interruptPending;
200 // If the interrupt ended up being cleared before being handled
201 bool clearInterrupt;
202
203 //////////// For IEW //////////////////
204 // Communication specifically to the IQ to tell the IQ that it can
205 // schedule a non-speculative instruction.
206 InstSeqNum nonSpecSeqNum;
207
208 // Hack for now to send back an uncached access to the IEW stage.
209 bool uncached;
210 DynInstPtr uncachedLoad;
211
212 };
213
214 commitComm commitInfo[Impl::MaxThreads];
215
216 bool decodeBlock[Impl::MaxThreads];
217 bool decodeUnblock[Impl::MaxThreads];
218 bool renameBlock[Impl::MaxThreads];
219 bool renameUnblock[Impl::MaxThreads];
220 bool iewBlock[Impl::MaxThreads];
221 bool iewUnblock[Impl::MaxThreads];
222 bool commitBlock[Impl::MaxThreads];
223 bool commitUnblock[Impl::MaxThreads];
224};
225
226#endif //__CPU_O3_COMM_HH__