base.cc (10553:c1ad57c53a36) base.cc (10653:e3fc6bc7f97e)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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113 if (numThreads != 1)
114 fatal("KVM: Multithreading not supported");
115
116 tc->initMemProxies(tc);
117
118 // initialize CPU, including PC
119 if (FullSystem && !switchedOut())
120 TheISA::initCPU(tc, tc->contextId());
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 104 unchanged lines hidden (view full) ---

113 if (numThreads != 1)
114 fatal("KVM: Multithreading not supported");
115
116 tc->initMemProxies(tc);
117
118 // initialize CPU, including PC
119 if (FullSystem && !switchedOut())
120 TheISA::initCPU(tc, tc->contextId());
121
122 mmio_req.setThreadContext(tc->contextId(), 0);
123}
124
125void
126BaseKvmCPU::startup()
127{
128 const BaseKvmCPUParams * const p(
129 dynamic_cast<const BaseKvmCPUParams *>(params()));
130

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990}
991
992Tick
993BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
994{
995 ThreadContext *tc(thread->getTC());
996 syncThreadContext();
997
121}
122
123void
124BaseKvmCPU::startup()
125{
126 const BaseKvmCPUParams * const p(
127 dynamic_cast<const BaseKvmCPUParams *>(params()));
128

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988}
989
990Tick
991BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
992{
993 ThreadContext *tc(thread->getTC());
994 syncThreadContext();
995
998 mmio_req.setPhys(paddr, size, Request::UNCACHEABLE, dataMasterId());
996 Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId());
997 mmio_req.setThreadContext(tc->contextId(), 0);
999 // Some architectures do need to massage physical addresses a bit
1000 // before they are inserted into the memory system. This enables
1001 // APIC accesses on x86 and m5ops where supported through a MMIO
1002 // interface.
1003 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
1004 Fault fault(tc->getDTBPtr()->finalizePhysical(&mmio_req, tc, tlb_mode));
1005 if (fault != NoFault)
1006 warn("Finalization of MMIO address failed: %s\n", fault->name());

--- 268 unchanged lines hidden --- 		998 // Some architectures do need to massage physical addresses a bit
999 // before they are inserted into the memory system. This enables
1000 // APIC accesses on x86 and m5ops where supported through a MMIO
1001 // interface.
1002 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
1003 Fault fault(tc->getDTBPtr()->finalizePhysical(&mmio_req, tc, tlb_mode));
1004 if (fault != NoFault)
1005 warn("Finalization of MMIO address failed: %s\n", fault->name());

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