cpu_impl.hh (9918:2c7219e2d999) cpu_impl.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 592 unchanged lines hidden (view full) ---

601 RegIndex idx = inst->destRegIdx(start_idx);
602 switch (regIdxToClass(idx)) {
603 case IntRegClass:
604 thread->setIntReg(idx, mismatch_val);
605 break;
606 case FloatRegClass:
607 thread->setFloatRegBits(idx, mismatch_val);
608 break;
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 592 unchanged lines hidden (view full) ---

601 RegIndex idx = inst->destRegIdx(start_idx);
602 switch (regIdxToClass(idx)) {
603 case IntRegClass:
604 thread->setIntReg(idx, mismatch_val);
605 break;
606 case FloatRegClass:
607 thread->setFloatRegBits(idx, mismatch_val);
608 break;
609 case CCRegClass:
610 thread->setCCReg(idx, mismatch_val);
611 break;
609 case MiscRegClass:
610 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
611 mismatch_val);
612 break;
613 }
614 }
615 start_idx++;
616 uint64_t res = 0;
617 for (int i = start_idx; i < inst->numDestRegs(); i++) {
618 RegIndex idx = inst->destRegIdx(i);
619 inst->template popResult<uint64_t>(res);
620 switch (regIdxToClass(idx)) {
621 case IntRegClass:
622 thread->setIntReg(idx, res);
623 break;
624 case FloatRegClass:
625 thread->setFloatRegBits(idx, res);
626 break;
612 case MiscRegClass:
613 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
614 mismatch_val);
615 break;
616 }
617 }
618 start_idx++;
619 uint64_t res = 0;
620 for (int i = start_idx; i < inst->numDestRegs(); i++) {
621 RegIndex idx = inst->destRegIdx(i);
622 inst->template popResult<uint64_t>(res);
623 switch (regIdxToClass(idx)) {
624 case IntRegClass:
625 thread->setIntReg(idx, res);
626 break;
627 case FloatRegClass:
628 thread->setFloatRegBits(idx, res);
629 break;
630 case CCRegClass:
631 thread->setCCReg(idx, res);
632 break;
627 case MiscRegClass:
628 // Try to get the proper misc register index for ARM here...
629 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
630 break;
631 // else Register is out of range...
632 }
633 }
634}

--- 46 unchanged lines hidden --- 		633 case MiscRegClass:
634 // Try to get the proper misc register index for ARM here...
635 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
636 break;
637 // else Register is out of range...
638 }
639 }
640}

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