cpu_impl.hh (3484:9b7ac1654430) cpu_impl.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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381 // checked simultaneously with the execution of the instruction.
382 // This is because other valid instructions may have modified
383 // these registers in the meantime, and their values are not
384 // stored within the DynInst.
385 while (!miscRegIdxs.empty()) {
386 int misc_reg_idx = miscRegIdxs.front();
387 miscRegIdxs.pop();
388
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 372 unchanged lines hidden (view full) ---

381 // checked simultaneously with the execution of the instruction.
382 // This is because other valid instructions may have modified
383 // these registers in the meantime, and their values are not
384 // stored within the DynInst.
385 while (!miscRegIdxs.empty()) {
386 int misc_reg_idx = miscRegIdxs.front();
387 miscRegIdxs.pop();
388
389 if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
390 thread->readMiscReg(misc_reg_idx)) {
389 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
390 thread->readMiscRegNoEffect(misc_reg_idx)) {
391 warn("%lli: Misc reg idx %i (side effect) does not match! "
392 "Inst: %#x, checker: %#x",
393 curTick, misc_reg_idx,
391 warn("%lli: Misc reg idx %i (side effect) does not match! "
392 "Inst: %#x, checker: %#x",
393 curTick, misc_reg_idx,
394 inst->tcBase()->readMiscReg(misc_reg_idx),
395 thread->readMiscReg(misc_reg_idx));
394 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
395 thread->readMiscRegNoEffect(misc_reg_idx));
396 handleError(inst);
397 }
398 }
399}
400
401template <class DynInstPtr>
402void
403Checker<DynInstPtr>::validateState()

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427Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
428{
429 RegIndex idx = inst->destRegIdx(0);
430 if (idx < TheISA::FP_Base_DepTag) {
431 thread->setIntReg(idx, inst->readIntResult());
432 } else if (idx < TheISA::Fpcr_DepTag) {
433 thread->setFloatRegBits(idx, inst->readIntResult());
434 } else {
396 handleError(inst);
397 }
398 }
399}
400
401template <class DynInstPtr>
402void
403Checker<DynInstPtr>::validateState()

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427Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
428{
429 RegIndex idx = inst->destRegIdx(0);
430 if (idx < TheISA::FP_Base_DepTag) {
431 thread->setIntReg(idx, inst->readIntResult());
432 } else if (idx < TheISA::Fpcr_DepTag) {
433 thread->setFloatRegBits(idx, inst->readIntResult());
434 } else {
435 thread->setMiscReg(idx, inst->readIntResult());
435 thread->setMiscRegNoEffect(idx, inst->readIntResult());
436 }
437}
438
439template <class DynInstPtr>
440void
441Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
442{
443 cprintf("Error detected, instruction information:\n");

--- 40 unchanged lines hidden --- 		436 }
437}
438
439template <class DynInstPtr>
440void
441Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
442{
443 cprintf("Error detected, instruction information:\n");

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