cpu_impl.hh (12749:223c83ed9979) cpu_impl.hh (13429:a1e199fd8122)
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 110 unchanged lines hidden (view full) ---

119 }
120 boundaryInst = NULL;
121 thread->decoder.reset();
122 curMacroStaticInst = StaticInst::nullStaticInstPtr;
123}
124
125template <class Impl>
126void
1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 110 unchanged lines hidden (view full) ---

119 }
120 boundaryInst = NULL;
121 thread->decoder.reset();
122 curMacroStaticInst = StaticInst::nullStaticInstPtr;
123}
124
125template <class Impl>
126void
127Checker::verify(DynInstPtr &completed_inst)
127Checker<Impl>::verify(const DynInstPtr &completed_inst)
128{
129 DynInstPtr inst;
130
131 // Make sure serializing instructions are actually
132 // seen as serializing to commit. instList should be
133 // empty in these cases.
134 if ((completed_inst->isSerializing() ||
135 completed_inst->isSerializeBefore()) &&

--- 315 unchanged lines hidden (view full) ---

451template <class Impl>
452void
453Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
454{
455}
456
457template <class Impl>
458void
128{
129 DynInstPtr inst;
130
131 // Make sure serializing instructions are actually
132 // seen as serializing to commit. instList should be
133 // empty in these cases.
134 if ((completed_inst->isSerializing() ||
135 completed_inst->isSerializeBefore()) &&

--- 315 unchanged lines hidden (view full) ---

451template <class Impl>
452void
453Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
454{
455}
456
457template <class Impl>
458void
459Checker::validateInst(DynInstPtr &inst)
459Checker<Impl>::validateInst(const DynInstPtr &inst)
460{
461 if (inst->instAddr() != thread->instAddr()) {
462 warn("%lli: PCs do not match! Inst: %s, checker: %s",
463 curTick(), inst->pcState(), thread->pcState());
464 if (changedPC) {
465 warn("%lli: Changed PCs recently, may not be an error",
466 curTick());
467 } else {

--- 4 unchanged lines hidden (view full) ---

472 if (curStaticInst != inst->staticInst) {
473 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
474 curStaticInst->getName(), inst->staticInst->getName());
475 }
476}
477
478template <class Impl>
479void
460{
461 if (inst->instAddr() != thread->instAddr()) {
462 warn("%lli: PCs do not match! Inst: %s, checker: %s",
463 curTick(), inst->pcState(), thread->pcState());
464 if (changedPC) {
465 warn("%lli: Changed PCs recently, may not be an error",
466 curTick());
467 } else {

--- 4 unchanged lines hidden (view full) ---

472 if (curStaticInst != inst->staticInst) {
473 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
474 curStaticInst->getName(), inst->staticInst->getName());
475 }
476}
477
478template <class Impl>
479void
480Checker::validateExecution(DynInstPtr &inst)
480Checker<Impl>::validateExecution(const DynInstPtr &inst)
481{
482 InstResult checker_val;
483 InstResult inst_val;
484 int idx = -1;
485 bool result_mismatch = false;
486 bool scalar_mismatch = false;
487 bool vector_mismatch = false;
488

--- 101 unchanged lines hidden (view full) ---

590 // Also advance the PC. Hopefully no PC-based events happened.
591 advancePC(NoFault);
592 updateThisCycle = false;
593 }
594}
595
596template <class Impl>
597void
481{
482 InstResult checker_val;
483 InstResult inst_val;
484 int idx = -1;
485 bool result_mismatch = false;
486 bool scalar_mismatch = false;
487 bool vector_mismatch = false;
488

--- 101 unchanged lines hidden (view full) ---

590 // Also advance the PC. Hopefully no PC-based events happened.
591 advancePC(NoFault);
592 updateThisCycle = false;
593 }
594}
595
596template <class Impl>
597void
598Checker<Impl>::copyResult(DynInstPtr &inst, const InstResult& mismatch_val,
599 int start_idx)
598Checker<Impl>::copyResult(const DynInstPtr &inst,
599 const InstResult& mismatch_val, int start_idx)
600{
601 // We've already popped one dest off the queue,
602 // so do the fix-up then start with the next dest reg;
603 if (start_idx >= 0) {
604 const RegId& idx = inst->destRegIdx(start_idx);
605 switch (idx.classValue()) {
606 case IntRegClass:
607 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");

--- 59 unchanged lines hidden (view full) ---

667 default:
668 panic("Unknown register class: %d", (int)idx.classValue());
669 }
670 }
671}
672
673template <class Impl>
674void
600{
601 // We've already popped one dest off the queue,
602 // so do the fix-up then start with the next dest reg;
603 if (start_idx >= 0) {
604 const RegId& idx = inst->destRegIdx(start_idx);
605 switch (idx.classValue()) {
606 case IntRegClass:
607 panic_if(!mismatch_val.isScalar(), "Unexpected type of result");

--- 59 unchanged lines hidden (view full) ---

667 default:
668 panic("Unknown register class: %d", (int)idx.classValue());
669 }
670 }
671}
672
673template <class Impl>
674void
675Checker::dumpAndExit(DynInstPtr &inst)
675Checker<Impl>::dumpAndExit(const DynInstPtr &inst)
676{
677 cprintf("Error detected, instruction information:\n");
678 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
679 "Completed:%i\n",
680 inst->pcState(),
681 inst->nextInstAddr(),
682 inst->seqNum,
683 inst->threadNumber,

--- 36 unchanged lines hidden --- 		676{
677 cprintf("Error detected, instruction information:\n");
678 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
679 "Completed:%i\n",
680 inst->pcState(),
681 inst->nextInstAddr(),
682 inst->seqNum,
683 inst->threadNumber,

--- 36 unchanged lines hidden ---