cpu_impl.hh (12104:edd63f9c6184) cpu_impl.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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590template <class Impl>
591void
592Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
593 int start_idx)
594{
595 // We've already popped one dest off the queue,
596 // so do the fix-up then start with the next dest reg;
597 if (start_idx >= 0) {
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 581 unchanged lines hidden (view full) ---

590template <class Impl>
591void
592Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
593 int start_idx)
594{
595 // We've already popped one dest off the queue,
596 // so do the fix-up then start with the next dest reg;
597 if (start_idx >= 0) {
598 RegId idx = inst->destRegIdx(start_idx);
599 switch (idx.regClass) {
598 const RegId& idx = inst->destRegIdx(start_idx);
599 switch (idx.classValue()) {
600 case IntRegClass:
600 case IntRegClass:
601 thread->setIntReg(idx.regIdx, mismatch_val);
601 thread->setIntReg(idx.index(), mismatch_val);
602 break;
603 case FloatRegClass:
602 break;
603 case FloatRegClass:
604 thread->setFloatRegBits(idx.regIdx, mismatch_val);
604 thread->setFloatRegBits(idx.index(), mismatch_val);
605 break;
606 case CCRegClass:
605 break;
606 case CCRegClass:
607 thread->setCCReg(idx.regIdx, mismatch_val);
607 thread->setCCReg(idx.index(), mismatch_val);
608 break;
609 case MiscRegClass:
608 break;
609 case MiscRegClass:
610 thread->setMiscReg(idx.regIdx, mismatch_val);
610 thread->setMiscReg(idx.index(), mismatch_val);
611 break;
612 }
613 }
614 start_idx++;
615 uint64_t res = 0;
616 for (int i = start_idx; i < inst->numDestRegs(); i++) {
611 break;
612 }
613 }
614 start_idx++;
615 uint64_t res = 0;
616 for (int i = start_idx; i < inst->numDestRegs(); i++) {
617 RegId idx = inst->destRegIdx(i);
617 const RegId& idx = inst->destRegIdx(i);
618 inst->template popResult<uint64_t>(res);
618 inst->template popResult<uint64_t>(res);
619 switch (idx.regClass) {
619 switch (idx.classValue()) {
620 case IntRegClass:
620 case IntRegClass:
621 thread->setIntReg(idx.regIdx, res);
621 thread->setIntReg(idx.index(), res);
622 break;
623 case FloatRegClass:
622 break;
623 case FloatRegClass:
624 thread->setFloatRegBits(idx.regIdx, res);
624 thread->setFloatRegBits(idx.index(), res);
625 break;
626 case CCRegClass:
625 break;
626 case CCRegClass:
627 thread->setCCReg(idx.regIdx, res);
627 thread->setCCReg(idx.index(), res);
628 break;
629 case MiscRegClass:
630 // Try to get the proper misc register index for ARM here...
628 break;
629 case MiscRegClass:
630 // Try to get the proper misc register index for ARM here...
631 thread->setMiscReg(idx.regIdx, res);
631 thread->setMiscReg(idx.index(), res);
632 break;
633 // else Register is out of range...
634 }
635 }
636}
637
638template <class Impl>
639void

--- 45 unchanged lines hidden --- 		632 break;
633 // else Register is out of range...
634 }
635 }
636}
637
638template <class Impl>
639void

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