cpu_impl.hh (10934:5af8f40d8f2c) cpu_impl.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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486 uint64_t inst_val;
487 int idx = -1;
488 bool result_mismatch = false;
489
490 if (inst->isUnverifiable()) {
491 // Unverifiable instructions assume they were executed
492 // properly by the CPU. Grab the result from the
493 // instruction and write it to the register.
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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486 uint64_t inst_val;
487 int idx = -1;
488 bool result_mismatch = false;
489
490 if (inst->isUnverifiable()) {
491 // Unverifiable instructions assume they were executed
492 // properly by the CPU. Grab the result from the
493 // instruction and write it to the register.
494 Result r;
495 r.integer = 0;
496 copyResult(inst, r, idx);
494 copyResult(inst, 0, idx);
497 } else if (inst->numDestRegs() > 0 && !result.empty()) {
498 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
499 inst->numDestRegs(), result.size());
500 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
501 result.front().get(checker_val);
502 result.pop();
503 inst_val = 0;
504 inst->template popResult<uint64_t>(inst_val);

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522 // It's useful to verify load values from memory, but in MP
523 // systems the value obtained at execute may be different than
524 // the value obtained at completion. Similarly DMA can
525 // present the same problem on even UP systems. Thus there is
526 // the option to only warn on loads having a result error.
527 // The load/store queue in Detailed CPU can also cause problems
528 // if load/store forwarding is allowed.
529 if (inst->isLoad() && warnOnlyOnLoadError) {
495 } else if (inst->numDestRegs() > 0 && !result.empty()) {
496 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
497 inst->numDestRegs(), result.size());
498 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
499 result.front().get(checker_val);
500 result.pop();
501 inst_val = 0;
502 inst->template popResult<uint64_t>(inst_val);

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520 // It's useful to verify load values from memory, but in MP
521 // systems the value obtained at execute may be different than
522 // the value obtained at completion. Similarly DMA can
523 // present the same problem on even UP systems. Thus there is
524 // the option to only warn on loads having a result error.
525 // The load/store queue in Detailed CPU can also cause problems
526 // if load/store forwarding is allowed.
527 if (inst->isLoad() && warnOnlyOnLoadError) {
530 Result r;
531 r.integer = inst_val;
532 copyResult(inst, r, idx);
528 copyResult(inst, inst_val, idx);
533 } else {
534 handleError(inst);
535 }
536 }
537
538 if (inst->nextInstAddr() != thread->nextInstAddr()) {
539 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
540 "checker: %#x",

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589 // Also advance the PC. Hopefully no PC-based events happened.
590 advancePC(NoFault);
591 updateThisCycle = false;
592 }
593}
594
595template <class Impl>
596void
529 } else {
530 handleError(inst);
531 }
532 }
533
534 if (inst->nextInstAddr() != thread->nextInstAddr()) {
535 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
536 "checker: %#x",

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585 // Also advance the PC. Hopefully no PC-based events happened.
586 advancePC(NoFault);
587 updateThisCycle = false;
588 }
589}
590
591template <class Impl>
592void
597Checker<Impl>::copyResult(DynInstPtr &inst, Result mismatch_val,
593Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
598 int start_idx)
599{
600 // We've already popped one dest off the queue,
601 // so do the fix-up then start with the next dest reg;
602 if (start_idx >= 0) {
603 RegIndex idx = inst->destRegIdx(start_idx);
604 switch (regIdxToClass(idx)) {
605 case IntRegClass:
594 int start_idx)
595{
596 // We've already popped one dest off the queue,
597 // so do the fix-up then start with the next dest reg;
598 if (start_idx >= 0) {
599 RegIndex idx = inst->destRegIdx(start_idx);
600 switch (regIdxToClass(idx)) {
601 case IntRegClass:
606 thread->setIntReg(idx, mismatch_val.integer);
602 thread->setIntReg(idx, mismatch_val);
607 break;
608 case FloatRegClass:
603 break;
604 case FloatRegClass:
609 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base,
610 mismatch_val.integer);
605 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
611 break;
612 case CCRegClass:
606 break;
607 case CCRegClass:
613 thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val.integer);
608 thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
614 break;
609 break;
615 case VectorRegClass:
616 thread->setVectorReg(idx - TheISA::Vector_Reg_Base,
617 mismatch_val.vector);
618 break;
619 case MiscRegClass:
620 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
610 case MiscRegClass:
611 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
621 mismatch_val.integer);
612 mismatch_val);
622 break;
623 }
624 }
613 break;
614 }
615 }
625
626 start_idx++;
616 start_idx++;
617 uint64_t res = 0;
627 for (int i = start_idx; i < inst->numDestRegs(); i++) {
628 RegIndex idx = inst->destRegIdx(i);
618 for (int i = start_idx; i < inst->numDestRegs(); i++) {
619 RegIndex idx = inst->destRegIdx(i);
620 inst->template popResult<uint64_t>(res);
629 switch (regIdxToClass(idx)) {
621 switch (regIdxToClass(idx)) {
630 case IntRegClass: {
631 uint64_t res = 0;
632 inst->template popResult<uint64_t>(res);
633 thread->setIntReg(idx, res);
634 }
635 break;
636
637 case FloatRegClass: {
638 uint64_t res = 0;
639 inst->template popResult<uint64_t>(res);
640 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
641 }
642 break;
643
644 case CCRegClass: {
645 uint64_t res = 0;
646 inst->template popResult<uint64_t>(res);
647 thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
648 }
649 break;
650
651 case VectorRegClass: {
652 VectorReg res;
653 inst->template popResult<VectorReg>(res);
654 thread->setVectorReg(idx - TheISA::Vector_Reg_Base, res);
655 }
656 break;
657
658 case MiscRegClass: {
659 // Try to get the proper misc register index for ARM here...
660 uint64_t res = 0;
661 inst->template popResult<uint64_t>(res);
662 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
663 }
664 break;
622 case IntRegClass:
623 thread->setIntReg(idx, res);
624 break;
625 case FloatRegClass:
626 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
627 break;
628 case CCRegClass:
629 thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
630 break;
631 case MiscRegClass:
632 // Try to get the proper misc register index for ARM here...
633 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
634 break;
665 // else Register is out of range...
666 }
667 }
668}
669
670template <class Impl>
671void
672Checker<Impl>::dumpAndExit(DynInstPtr &inst)

--- 44 unchanged lines hidden --- 		635 // else Register is out of range...
636 }
637 }
638}
639
640template <class Impl>
641void
642Checker<Impl>::dumpAndExit(DynInstPtr &inst)

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