1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 593 unchanged lines hidden (view full) --- 602 // so do the fix-up then start with the next dest reg; 603 if (start_idx >= 0) { 604 RegIndex idx = inst->destRegIdx(start_idx); 605 switch (regIdxToClass(idx)) { 606 case IntRegClass: 607 thread->setIntReg(idx, mismatch_val); 608 break; 609 case FloatRegClass: |
610 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val); |
611 break; 612 case CCRegClass: |
613 thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val); |
614 break; 615 case MiscRegClass: 616 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, 617 mismatch_val); 618 break; 619 } 620 } 621 start_idx++; 622 uint64_t res = 0; 623 for (int i = start_idx; i < inst->numDestRegs(); i++) { 624 RegIndex idx = inst->destRegIdx(i); 625 inst->template popResult<uint64_t>(res); 626 switch (regIdxToClass(idx)) { 627 case IntRegClass: 628 thread->setIntReg(idx, res); 629 break; 630 case FloatRegClass: |
631 thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res); |
632 break; 633 case CCRegClass: |
634 thread->setCCReg(idx - TheISA::CC_Reg_Base, res); |
635 break; 636 case MiscRegClass: 637 // Try to get the proper misc register index for ARM here... 638 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res); 639 break; 640 // else Register is out of range... 641 } 642 } --- 49 unchanged lines hidden --- |