1/* 2 * Copyright (c) 2011 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. |
4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 34 unchanged lines hidden (view full) --- 46#include <string> 47 48#include "arch/isa_traits.hh" 49#include "arch/vtophys.hh" 50#include "base/refcnt.hh" 51#include "config/the_isa.hh" 52#include "cpu/base_dyn_inst.hh" 53#include "cpu/exetrace.hh" |
54#include "cpu/reg_class.hh" |
55#include "cpu/simple_thread.hh" 56#include "cpu/static_inst.hh" 57#include "cpu/thread_context.hh" 58#include "cpu/checker/cpu.hh" 59#include "debug/Checker.hh" 60#include "sim/full_system.hh" 61#include "sim/sim_object.hh" 62#include "sim/stats.hh" --- 531 unchanged lines hidden (view full) --- 594void 595Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val, 596 int start_idx) 597{ 598 // We've already popped one dest off the queue, 599 // so do the fix-up then start with the next dest reg; 600 if (start_idx >= 0) { 601 RegIndex idx = inst->destRegIdx(start_idx); |
602 switch (regIdxToClass(idx)) { 603 case IntRegClass: |
604 thread->setIntReg(idx, mismatch_val); |
605 break; 606 case FloatRegClass: |
607 thread->setFloatRegBits(idx, mismatch_val); |
608 break; 609 case MiscRegClass: |
610 thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, 611 mismatch_val); |
612 break; |
613 } 614 } 615 start_idx++; 616 uint64_t res = 0; 617 for (int i = start_idx; i < inst->numDestRegs(); i++) { 618 RegIndex idx = inst->destRegIdx(i); 619 inst->template popResult<uint64_t>(res); |
620 switch (regIdxToClass(idx)) { 621 case IntRegClass: |
622 thread->setIntReg(idx, res); |
623 break; 624 case FloatRegClass: |
625 thread->setFloatRegBits(idx, res); |
626 break; 627 case MiscRegClass: |
628 // Try to get the proper misc register index for ARM here... 629 thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res); |
630 break; 631 // else Register is out of range... 632 } |
633 } 634} 635 636template <class Impl> 637void 638Checker<Impl>::dumpAndExit(DynInstPtr &inst) 639{ 640 cprintf("Error detected, instruction information:\n"); --- 40 unchanged lines hidden --- |