598,599c598,599
< RegId idx = inst->destRegIdx(start_idx);
< switch (idx.regClass) {
---
> const RegId& idx = inst->destRegIdx(start_idx);
> switch (idx.classValue()) {
601c601
< thread->setIntReg(idx.regIdx, mismatch_val);
---
> thread->setIntReg(idx.index(), mismatch_val);
604c604
< thread->setFloatRegBits(idx.regIdx, mismatch_val);
---
> thread->setFloatRegBits(idx.index(), mismatch_val);
607c607
< thread->setCCReg(idx.regIdx, mismatch_val);
---
> thread->setCCReg(idx.index(), mismatch_val);
610c610
< thread->setMiscReg(idx.regIdx, mismatch_val);
---
> thread->setMiscReg(idx.index(), mismatch_val);
617c617
< RegId idx = inst->destRegIdx(i);
---
> const RegId& idx = inst->destRegIdx(i);
619c619
< switch (idx.regClass) {
---
> switch (idx.classValue()) {
621c621
< thread->setIntReg(idx.regIdx, res);
---
> thread->setIntReg(idx.index(), res);
624c624
< thread->setFloatRegBits(idx.regIdx, res);
---
> thread->setFloatRegBits(idx.index(), res);
627c627
< thread->setCCReg(idx.regIdx, res);
---
> thread->setCCReg(idx.index(), res);
631c631
< thread->setMiscReg(idx.regIdx, res);
---
> thread->setMiscReg(idx.index(), res);