494,496c494
< Result r;
< r.integer = 0;
< copyResult(inst, r, idx);
---
> copyResult(inst, 0, idx);
530,532c528
< Result r;
< r.integer = inst_val;
< copyResult(inst, r, idx);
---
> copyResult(inst, inst_val, idx);
597c593
< Checker<Impl>::copyResult(DynInstPtr &inst, Result mismatch_val,
---
> Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
606c602
< thread->setIntReg(idx, mismatch_val.integer);
---
> thread->setIntReg(idx, mismatch_val);
609,610c605
< thread->setFloatRegBits(idx - TheISA::FP_Reg_Base,
< mismatch_val.integer);
---
> thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
613c608
< thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val.integer);
---
> thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
615,618d609
< case VectorRegClass:
< thread->setVectorReg(idx - TheISA::Vector_Reg_Base,
< mismatch_val.vector);
< break;
621c612
< mismatch_val.integer);
---
> mismatch_val);
625d615
<
626a617
> uint64_t res = 0;
628a620
> inst->template popResult<uint64_t>(res);
630,664c622,634
< case IntRegClass: {
< uint64_t res = 0;
< inst->template popResult<uint64_t>(res);
< thread->setIntReg(idx, res);
< }
< break;
<
< case FloatRegClass: {
< uint64_t res = 0;
< inst->template popResult<uint64_t>(res);
< thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
< }
< break;
<
< case CCRegClass: {
< uint64_t res = 0;
< inst->template popResult<uint64_t>(res);
< thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
< }
< break;
<
< case VectorRegClass: {
< VectorReg res;
< inst->template popResult<VectorReg>(res);
< thread->setVectorReg(idx - TheISA::Vector_Reg_Base, res);
< }
< break;
<
< case MiscRegClass: {
< // Try to get the proper misc register index for ARM here...
< uint64_t res = 0;
< inst->template popResult<uint64_t>(res);
< thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
< }
< break;
---
> case IntRegClass:
> thread->setIntReg(idx, res);
> break;
> case FloatRegClass:
> thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
> break;
> case CCRegClass:
> thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
> break;
> case MiscRegClass:
> // Try to get the proper misc register index for ARM here...
> thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
> break;