45#include <list>
46#include <string>
47
48#include "arch/isa_traits.hh"
49#include "arch/vtophys.hh"
50#include "base/refcnt.hh"
51#include "config/the_isa.hh"
52#include "cpu/base_dyn_inst.hh"
53#include "cpu/exetrace.hh"
54#include "cpu/reg_class.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/static_inst.hh"
57#include "cpu/thread_context.hh"
58#include "cpu/checker/cpu.hh"
59#include "debug/Checker.hh"
60#include "sim/full_system.hh"
61#include "sim/sim_object.hh"
62#include "sim/stats.hh"
63
64using namespace std;
65using namespace TheISA;
66
67template <class Impl>
68void
69Checker<Impl>::advancePC(Fault fault)
70{
71 if (fault != NoFault) {
72 curMacroStaticInst = StaticInst::nullStaticInstPtr;
73 fault->invoke(tc, curStaticInst);
74 thread->decoder.reset();
75 } else {
76 if (curStaticInst) {
77 if (curStaticInst->isLastMicroop())
78 curMacroStaticInst = StaticInst::nullStaticInstPtr;
79 TheISA::PCState pcState = thread->pcState();
80 TheISA::advancePC(pcState, curStaticInst);
81 thread->pcState(pcState);
82 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
83 }
84 }
85}
86//////////////////////////////////////////////////
87
88template <class Impl>
89void
90Checker<Impl>::handlePendingInt()
91{
92 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
93 thread->pcState(), instList.size());
94 DynInstPtr boundaryInst = NULL;
95 if (!instList.empty()) {
96 // Set the instructions as completed and verify as much as possible.
97 DynInstPtr inst;
98 typename std::list<DynInstPtr>::iterator itr;
99
100 for (itr = instList.begin(); itr != instList.end(); itr++) {
101 (*itr)->setCompleted();
102 }
103
104 inst = instList.front();
105 boundaryInst = instList.back();
106 verify(inst); // verify the instructions
107 inst = NULL;
108 }
109 if ((!boundaryInst && curMacroStaticInst &&
110 curStaticInst->isDelayedCommit() &&
111 !curStaticInst->isLastMicroop()) ||
112 (boundaryInst && boundaryInst->isDelayedCommit() &&
113 !boundaryInst->isLastMicroop())) {
114 panic("%lli: Trying to take an interrupt in middle of "
115 "a non-interuptable instruction!", curTick());
116 }
117 boundaryInst = NULL;
118 thread->decoder.reset();
119 curMacroStaticInst = StaticInst::nullStaticInstPtr;
120}
121
122template <class Impl>
123void
124Checker<Impl>::verify(DynInstPtr &completed_inst)
125{
126 DynInstPtr inst;
127
128 // Make sure serializing instructions are actually
129 // seen as serializing to commit. instList should be
130 // empty in these cases.
131 if ((completed_inst->isSerializing() ||
132 completed_inst->isSerializeBefore()) &&
133 (!instList.empty() ?
134 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
135 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
136 " entering instList with other instructions\n", curTick(),
137 completed_inst->seqNum, completed_inst->pcState());
138 }
139
140 // Either check this instruction, or add it to a list of
141 // instructions waiting to be checked. Instructions must be
142 // checked in program order, so if a store has committed yet not
143 // completed, there may be some instructions that are waiting
144 // behind it that have completed and must be checked.
145 if (!instList.empty()) {
146 if (youngestSN < completed_inst->seqNum) {
147 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
148 completed_inst->seqNum, completed_inst->pcState());
149 instList.push_back(completed_inst);
150 youngestSN = completed_inst->seqNum;
151 }
152
153 if (!instList.front()->isCompleted()) {
154 return;
155 } else {
156 inst = instList.front();
157 instList.pop_front();
158 }
159 } else {
160 if (!completed_inst->isCompleted()) {
161 if (youngestSN < completed_inst->seqNum) {
162 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
163 completed_inst->seqNum, completed_inst->pcState());
164 instList.push_back(completed_inst);
165 youngestSN = completed_inst->seqNum;
166 }
167 return;
168 } else {
169 if (youngestSN < completed_inst->seqNum) {
170 inst = completed_inst;
171 youngestSN = completed_inst->seqNum;
172 } else {
173 return;
174 }
175 }
176 }
177
178 // Make sure a serializing instruction is actually seen as
179 // serializing. instList should be empty here
180 if (inst->isSerializeAfter() && !instList.empty()) {
181 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
182 " exiting instList with other instructions\n", curTick(),
183 completed_inst->seqNum, completed_inst->pcState());
184 }
185 unverifiedInst = inst;
186 inst = NULL;
187
188 // Try to check all instructions that are completed, ending if we
189 // run out of instructions to check or if an instruction is not
190 // yet completed.
191 while (1) {
192 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
193 unverifiedInst->seqNum, unverifiedInst->pcState());
194 unverifiedReq = NULL;
195 unverifiedReq = unverifiedInst->reqToVerify;
196 unverifiedMemData = unverifiedInst->memData;
197 // Make sure results queue is empty
198 while (!result.empty()) {
199 result.pop();
200 }
201 numCycles++;
202
203 Fault fault = NoFault;
204
205 // maintain $r0 semantics
206 thread->setIntReg(ZeroReg, 0);
207#if THE_ISA == ALPHA_ISA
208 thread->setFloatReg(ZeroReg, 0.0);
209#endif
210
211 // Check if any recent PC changes match up with anything we
212 // expect to happen. This is mostly to check if traps or
213 // PC-based events have occurred in both the checker and CPU.
214 if (changedPC) {
215 DPRINTF(Checker, "Changed PC recently to %s\n",
216 thread->pcState());
217 if (willChangePC) {
218 if (newPCState == thread->pcState()) {
219 DPRINTF(Checker, "Changed PC matches expected PC\n");
220 } else {
221 warn("%lli: Changed PC does not match expected PC, "
222 "changed: %s, expected: %s",
223 curTick(), thread->pcState(), newPCState);
224 CheckerCPU::handleError();
225 }
226 willChangePC = false;
227 }
228 changedPC = false;
229 }
230 if (changedNextPC) {
231 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
232 thread->nextInstAddr());
233 changedNextPC = false;
234 }
235
236 // Try to fetch the instruction
237 uint64_t fetchOffset = 0;
238 bool fetchDone = false;
239
240 while (!fetchDone) {
241 Addr fetch_PC = thread->instAddr();
242 fetch_PC = (fetch_PC & PCMask) + fetchOffset;
243
244 MachInst machInst;
245
246 // If not in the middle of a macro instruction
247 if (!curMacroStaticInst) {
248 // set up memory request for instruction fetch
249 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
250 sizeof(MachInst),
251 0,
252 masterId,
253 fetch_PC, thread->contextId(),
254 unverifiedInst->threadNumber);
255 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
256 Request::INST_FETCH, masterId, thread->instAddr());
257
258
259 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
260
261 if (fault != NoFault) {
262 if (unverifiedInst->getFault() == NoFault) {
263 // In this case the instruction was not a dummy
264 // instruction carrying an ITB fault. In the single
265 // threaded case the ITB should still be able to
266 // translate this instruction; in the SMT case it's
267 // possible that its ITB entry was kicked out.
268 warn("%lli: Instruction PC %s was not found in the "
269 "ITB!", curTick(), thread->pcState());
270 handleError(unverifiedInst);
271
272 // go to the next instruction
273 advancePC(NoFault);
274
275 // Give up on an ITB fault..
276 delete memReq;
277 unverifiedInst = NULL;
278 return;
279 } else {
280 // The instruction is carrying an ITB fault. Handle
281 // the fault and see if our results match the CPU on
282 // the next tick().
283 fault = unverifiedInst->getFault();
284 delete memReq;
285 break;
286 }
287 } else {
288 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
289
290 pkt->dataStatic(&machInst);
291 icachePort->sendFunctional(pkt);
292 machInst = gtoh(machInst);
293
294 delete memReq;
295 delete pkt;
296 }
297 }
298
299 if (fault == NoFault) {
300 TheISA::PCState pcState = thread->pcState();
301
302 if (isRomMicroPC(pcState.microPC())) {
303 fetchDone = true;
304 curStaticInst =
305 microcodeRom.fetchMicroop(pcState.microPC(), NULL);
306 } else if (!curMacroStaticInst) {
307 //We're not in the middle of a macro instruction
308 StaticInstPtr instPtr = NULL;
309
310 //Predecode, ie bundle up an ExtMachInst
311 //If more fetch data is needed, pass it in.
312 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
313 thread->decoder.moreBytes(pcState, fetchPC, machInst);
314
315 //If an instruction is ready, decode it.
316 //Otherwise, we'll have to fetch beyond the
317 //MachInst at the current pc.
318 if (thread->decoder.instReady()) {
319 fetchDone = true;
320 instPtr = thread->decoder.decode(pcState);
321 thread->pcState(pcState);
322 } else {
323 fetchDone = false;
324 fetchOffset += sizeof(TheISA::MachInst);
325 }
326
327 //If we decoded an instruction and it's microcoded,
328 //start pulling out micro ops
329 if (instPtr && instPtr->isMacroop()) {
330 curMacroStaticInst = instPtr;
331 curStaticInst =
332 instPtr->fetchMicroop(pcState.microPC());
333 } else {
334 curStaticInst = instPtr;
335 }
336 } else {
337 // Read the next micro op from the macro-op
338 curStaticInst =
339 curMacroStaticInst->fetchMicroop(pcState.microPC());
340 fetchDone = true;
341 }
342 }
343 }
344 // reset decoder on Checker
345 thread->decoder.reset();
346
347 // Check Checker and CPU get same instruction, and record
348 // any faults the CPU may have had.
349 Fault unverifiedFault;
350 if (fault == NoFault) {
351 unverifiedFault = unverifiedInst->getFault();
352
353 // Checks that the instruction matches what we expected it to be.
354 // Checks both the machine instruction and the PC.
355 validateInst(unverifiedInst);
356 }
357
358 // keep an instruction count
359 numInst++;
360
361
362 // Either the instruction was a fault and we should process the fault,
363 // or we should just go ahead execute the instruction. This assumes
364 // that the instruction is properly marked as a fault.
365 if (fault == NoFault) {
366 // Execute Checker instruction and trace
367 if (!unverifiedInst->isUnverifiable()) {
368 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
369 tc,
370 curStaticInst,
371 pcState(),
372 curMacroStaticInst);
373 fault = curStaticInst->execute(this, traceData);
374 if (traceData) {
375 traceData->dump();
376 delete traceData;
377 }
378 }
379
380 if (fault == NoFault && unverifiedFault == NoFault) {
381 thread->funcExeInst++;
382 // Checks to make sure instrution results are correct.
383 validateExecution(unverifiedInst);
384
385 if (curStaticInst->isLoad()) {
386 ++numLoad;
387 }
388 } else if (fault != NoFault && unverifiedFault == NoFault) {
389 panic("%lli: sn: %lli at PC: %s took a fault in checker "
390 "but not in driver CPU\n", curTick(),
391 unverifiedInst->seqNum, unverifiedInst->pcState());
392 } else if (fault == NoFault && unverifiedFault != NoFault) {
393 panic("%lli: sn: %lli at PC: %s took a fault in driver "
394 "CPU but not in checker\n", curTick(),
395 unverifiedInst->seqNum, unverifiedInst->pcState());
396 }
397 }
398
399 // Take any faults here
400 if (fault != NoFault) {
401 if (FullSystem) {
402 fault->invoke(tc, curStaticInst);
403 willChangePC = true;
404 newPCState = thread->pcState();
405 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
406 curMacroStaticInst = StaticInst::nullStaticInstPtr;
407 }
408 } else {
409 advancePC(fault);
410 }
411
412 if (FullSystem) {
413 // @todo: Determine if these should happen only if the
414 // instruction hasn't faulted. In the SimpleCPU case this may
415 // not be true, but in the O3 or Ozone case this may be true.
416 Addr oldpc;
417 int count = 0;
418 do {
419 oldpc = thread->instAddr();
420 system->pcEventQueue.service(tc);
421 count++;
422 } while (oldpc != thread->instAddr());
423 if (count > 1) {
424 willChangePC = true;
425 newPCState = thread->pcState();
426 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
427 }
428 }
429
430 // @todo: Optionally can check all registers. (Or just those
431 // that have been modified).
432 validateState();
433
434 // Continue verifying instructions if there's another completed
435 // instruction waiting to be verified.
436 if (instList.empty()) {
437 break;
438 } else if (instList.front()->isCompleted()) {
439 unverifiedInst = NULL;
440 unverifiedInst = instList.front();
441 instList.pop_front();
442 } else {
443 break;
444 }
445 }
446 unverifiedInst = NULL;
447}
448
449template <class Impl>
450void
451Checker<Impl>::switchOut()
452{
453 instList.clear();
454}
455
456template <class Impl>
457void
458Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
459{
460}
461
462template <class Impl>
463void
464Checker<Impl>::validateInst(DynInstPtr &inst)
465{
466 if (inst->instAddr() != thread->instAddr()) {
467 warn("%lli: PCs do not match! Inst: %s, checker: %s",
468 curTick(), inst->pcState(), thread->pcState());
469 if (changedPC) {
470 warn("%lli: Changed PCs recently, may not be an error",
471 curTick());
472 } else {
473 handleError(inst);
474 }
475 }
476
477 if (curStaticInst != inst->staticInst) {
478 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
479 curStaticInst->getName(), inst->staticInst->getName());
480 }
481}
482
483template <class Impl>
484void
485Checker<Impl>::validateExecution(DynInstPtr &inst)
486{
487 uint64_t checker_val;
488 uint64_t inst_val;
489 int idx = -1;
490 bool result_mismatch = false;
491
492 if (inst->isUnverifiable()) {
493 // Unverifiable instructions assume they were executed
494 // properly by the CPU. Grab the result from the
495 // instruction and write it to the register.
496 copyResult(inst, 0, idx);
497 } else if (inst->numDestRegs() > 0 && !result.empty()) {
498 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
499 inst->numDestRegs(), result.size());
500 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
501 result.front().get(checker_val);
502 result.pop();
503 inst_val = 0;
504 inst->template popResult<uint64_t>(inst_val);
505 if (checker_val != inst_val) {
506 result_mismatch = true;
507 idx = i;
508 break;
509 }
510 }
511 } // Checker CPU checks all the saved results in the dyninst passed by
512 // the cpu model being checked against the saved results present in
513 // the static inst executed in the Checker. Sometimes the number
514 // of saved results differs between the dyninst and static inst, but
515 // this is ok and not a bug. May be worthwhile to try and correct this.
516
517 if (result_mismatch) {
518 warn("%lli: Instruction results do not match! (Values may not "
519 "actually be integers) Inst: %#x, checker: %#x",
520 curTick(), inst_val, checker_val);
521
522 // It's useful to verify load values from memory, but in MP
523 // systems the value obtained at execute may be different than
524 // the value obtained at completion. Similarly DMA can
525 // present the same problem on even UP systems. Thus there is
526 // the option to only warn on loads having a result error.
527 // The load/store queue in Detailed CPU can also cause problems
528 // if load/store forwarding is allowed.
529 if (inst->isLoad() && warnOnlyOnLoadError) {
530 copyResult(inst, inst_val, idx);
531 } else {
532 handleError(inst);
533 }
534 }
535
536 if (inst->nextInstAddr() != thread->nextInstAddr()) {
537 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
538 "checker: %#x",
539 curTick(), inst->nextInstAddr(), thread->nextInstAddr());
540 handleError(inst);
541 }
542
543 // Checking side effect registers can be difficult if they are not
544 // checked simultaneously with the execution of the instruction.
545 // This is because other valid instructions may have modified
546 // these registers in the meantime, and their values are not
547 // stored within the DynInst.
548 while (!miscRegIdxs.empty()) {
549 int misc_reg_idx = miscRegIdxs.front();
550 miscRegIdxs.pop();
551
552 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
553 thread->readMiscRegNoEffect(misc_reg_idx)) {
554 warn("%lli: Misc reg idx %i (side effect) does not match! "
555 "Inst: %#x, checker: %#x",
556 curTick(), misc_reg_idx,
557 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
558 thread->readMiscRegNoEffect(misc_reg_idx));
559 handleError(inst);
560 }
561 }
562}
563
564
565// This function is weird, if it is called it means the Checker and
566// O3 have diverged, so panic is called for now. It may be useful
567// to resynch states and continue if the divergence is a false positive
568template <class Impl>
569void
570Checker<Impl>::validateState()
571{
572 if (updateThisCycle) {
573 // Change this back to warn if divergences end up being false positives
574 panic("%lli: Instruction PC %#x results didn't match up, copying all "
575 "registers from main CPU", curTick(), unverifiedInst->instAddr());
576
577 // Terribly convoluted way to make sure O3 model does not implode
578 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
579 unverifiedInst->thread->noSquashFromTC = true;
580
581 // Heavy-weight copying of all registers
582 thread->copyArchRegs(unverifiedInst->tcBase());
583 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
584
585 // Set curStaticInst to unverifiedInst->staticInst
586 curStaticInst = unverifiedInst->staticInst;
587 // Also advance the PC. Hopefully no PC-based events happened.
588 advancePC(NoFault);
589 updateThisCycle = false;
590 }
591}
592
593template <class Impl>
594void
595Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
596 int start_idx)
597{
598 // We've already popped one dest off the queue,
599 // so do the fix-up then start with the next dest reg;
600 if (start_idx >= 0) {
601 RegIndex idx = inst->destRegIdx(start_idx);
602 switch (regIdxToClass(idx)) {
603 case IntRegClass:
604 thread->setIntReg(idx, mismatch_val);
605 break;
606 case FloatRegClass:
607 thread->setFloatRegBits(idx, mismatch_val);
608 break;
609 case CCRegClass:
610 thread->setCCReg(idx, mismatch_val);
611 break;
612 case MiscRegClass:
613 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
614 mismatch_val);
615 break;
616 }
617 }
618 start_idx++;
619 uint64_t res = 0;
620 for (int i = start_idx; i < inst->numDestRegs(); i++) {
621 RegIndex idx = inst->destRegIdx(i);
622 inst->template popResult<uint64_t>(res);
623 switch (regIdxToClass(idx)) {
624 case IntRegClass:
625 thread->setIntReg(idx, res);
626 break;
627 case FloatRegClass:
628 thread->setFloatRegBits(idx, res);
629 break;
630 case CCRegClass:
631 thread->setCCReg(idx, res);
632 break;
633 case MiscRegClass:
634 // Try to get the proper misc register index for ARM here...
635 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
636 break;
637 // else Register is out of range...
638 }
639 }
640}
641
642template <class Impl>
643void
644Checker<Impl>::dumpAndExit(DynInstPtr &inst)
645{
646 cprintf("Error detected, instruction information:\n");
647 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
648 "Completed:%i\n",
649 inst->pcState(),
650 inst->nextInstAddr(),
651 inst->seqNum,
652 inst->threadNumber,
653 inst->isCompleted());
654 inst->dump();
655 CheckerCPU::dumpAndExit();
656}
657
658template <class Impl>
659void
660Checker<Impl>::dumpInsts()
661{
662 int num = 0;
663
664 InstListIt inst_list_it = --(instList.end());
665
666 cprintf("Inst list size: %i\n", instList.size());
667
668 while (inst_list_it != instList.end())
669 {
670 cprintf("Instruction:%i\n",
671 num);
672
673 cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
674 "Completed:%i\n",
675 (*inst_list_it)->pcState(),
676 (*inst_list_it)->seqNum,
677 (*inst_list_it)->threadNumber,
678 (*inst_list_it)->isCompleted());
679
680 cprintf("\n");
681
682 inst_list_it--;
683 ++num;
684 }
685
686}
| 48#include <list>
49#include <string>
50
51#include "arch/isa_traits.hh"
52#include "arch/vtophys.hh"
53#include "base/refcnt.hh"
54#include "config/the_isa.hh"
55#include "cpu/base_dyn_inst.hh"
56#include "cpu/exetrace.hh"
57#include "cpu/reg_class.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/static_inst.hh"
60#include "cpu/thread_context.hh"
61#include "cpu/checker/cpu.hh"
62#include "debug/Checker.hh"
63#include "sim/full_system.hh"
64#include "sim/sim_object.hh"
65#include "sim/stats.hh"
66
67using namespace std;
68using namespace TheISA;
69
70template <class Impl>
71void
72Checker<Impl>::advancePC(Fault fault)
73{
74 if (fault != NoFault) {
75 curMacroStaticInst = StaticInst::nullStaticInstPtr;
76 fault->invoke(tc, curStaticInst);
77 thread->decoder.reset();
78 } else {
79 if (curStaticInst) {
80 if (curStaticInst->isLastMicroop())
81 curMacroStaticInst = StaticInst::nullStaticInstPtr;
82 TheISA::PCState pcState = thread->pcState();
83 TheISA::advancePC(pcState, curStaticInst);
84 thread->pcState(pcState);
85 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
86 }
87 }
88}
89//////////////////////////////////////////////////
90
91template <class Impl>
92void
93Checker<Impl>::handlePendingInt()
94{
95 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
96 thread->pcState(), instList.size());
97 DynInstPtr boundaryInst = NULL;
98 if (!instList.empty()) {
99 // Set the instructions as completed and verify as much as possible.
100 DynInstPtr inst;
101 typename std::list<DynInstPtr>::iterator itr;
102
103 for (itr = instList.begin(); itr != instList.end(); itr++) {
104 (*itr)->setCompleted();
105 }
106
107 inst = instList.front();
108 boundaryInst = instList.back();
109 verify(inst); // verify the instructions
110 inst = NULL;
111 }
112 if ((!boundaryInst && curMacroStaticInst &&
113 curStaticInst->isDelayedCommit() &&
114 !curStaticInst->isLastMicroop()) ||
115 (boundaryInst && boundaryInst->isDelayedCommit() &&
116 !boundaryInst->isLastMicroop())) {
117 panic("%lli: Trying to take an interrupt in middle of "
118 "a non-interuptable instruction!", curTick());
119 }
120 boundaryInst = NULL;
121 thread->decoder.reset();
122 curMacroStaticInst = StaticInst::nullStaticInstPtr;
123}
124
125template <class Impl>
126void
127Checker<Impl>::verify(DynInstPtr &completed_inst)
128{
129 DynInstPtr inst;
130
131 // Make sure serializing instructions are actually
132 // seen as serializing to commit. instList should be
133 // empty in these cases.
134 if ((completed_inst->isSerializing() ||
135 completed_inst->isSerializeBefore()) &&
136 (!instList.empty() ?
137 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
138 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
139 " entering instList with other instructions\n", curTick(),
140 completed_inst->seqNum, completed_inst->pcState());
141 }
142
143 // Either check this instruction, or add it to a list of
144 // instructions waiting to be checked. Instructions must be
145 // checked in program order, so if a store has committed yet not
146 // completed, there may be some instructions that are waiting
147 // behind it that have completed and must be checked.
148 if (!instList.empty()) {
149 if (youngestSN < completed_inst->seqNum) {
150 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
151 completed_inst->seqNum, completed_inst->pcState());
152 instList.push_back(completed_inst);
153 youngestSN = completed_inst->seqNum;
154 }
155
156 if (!instList.front()->isCompleted()) {
157 return;
158 } else {
159 inst = instList.front();
160 instList.pop_front();
161 }
162 } else {
163 if (!completed_inst->isCompleted()) {
164 if (youngestSN < completed_inst->seqNum) {
165 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
166 completed_inst->seqNum, completed_inst->pcState());
167 instList.push_back(completed_inst);
168 youngestSN = completed_inst->seqNum;
169 }
170 return;
171 } else {
172 if (youngestSN < completed_inst->seqNum) {
173 inst = completed_inst;
174 youngestSN = completed_inst->seqNum;
175 } else {
176 return;
177 }
178 }
179 }
180
181 // Make sure a serializing instruction is actually seen as
182 // serializing. instList should be empty here
183 if (inst->isSerializeAfter() && !instList.empty()) {
184 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
185 " exiting instList with other instructions\n", curTick(),
186 completed_inst->seqNum, completed_inst->pcState());
187 }
188 unverifiedInst = inst;
189 inst = NULL;
190
191 // Try to check all instructions that are completed, ending if we
192 // run out of instructions to check or if an instruction is not
193 // yet completed.
194 while (1) {
195 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
196 unverifiedInst->seqNum, unverifiedInst->pcState());
197 unverifiedReq = NULL;
198 unverifiedReq = unverifiedInst->reqToVerify;
199 unverifiedMemData = unverifiedInst->memData;
200 // Make sure results queue is empty
201 while (!result.empty()) {
202 result.pop();
203 }
204 numCycles++;
205
206 Fault fault = NoFault;
207
208 // maintain $r0 semantics
209 thread->setIntReg(ZeroReg, 0);
210#if THE_ISA == ALPHA_ISA
211 thread->setFloatReg(ZeroReg, 0.0);
212#endif
213
214 // Check if any recent PC changes match up with anything we
215 // expect to happen. This is mostly to check if traps or
216 // PC-based events have occurred in both the checker and CPU.
217 if (changedPC) {
218 DPRINTF(Checker, "Changed PC recently to %s\n",
219 thread->pcState());
220 if (willChangePC) {
221 if (newPCState == thread->pcState()) {
222 DPRINTF(Checker, "Changed PC matches expected PC\n");
223 } else {
224 warn("%lli: Changed PC does not match expected PC, "
225 "changed: %s, expected: %s",
226 curTick(), thread->pcState(), newPCState);
227 CheckerCPU::handleError();
228 }
229 willChangePC = false;
230 }
231 changedPC = false;
232 }
233 if (changedNextPC) {
234 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
235 thread->nextInstAddr());
236 changedNextPC = false;
237 }
238
239 // Try to fetch the instruction
240 uint64_t fetchOffset = 0;
241 bool fetchDone = false;
242
243 while (!fetchDone) {
244 Addr fetch_PC = thread->instAddr();
245 fetch_PC = (fetch_PC & PCMask) + fetchOffset;
246
247 MachInst machInst;
248
249 // If not in the middle of a macro instruction
250 if (!curMacroStaticInst) {
251 // set up memory request for instruction fetch
252 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
253 sizeof(MachInst),
254 0,
255 masterId,
256 fetch_PC, thread->contextId(),
257 unverifiedInst->threadNumber);
258 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
259 Request::INST_FETCH, masterId, thread->instAddr());
260
261
262 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
263
264 if (fault != NoFault) {
265 if (unverifiedInst->getFault() == NoFault) {
266 // In this case the instruction was not a dummy
267 // instruction carrying an ITB fault. In the single
268 // threaded case the ITB should still be able to
269 // translate this instruction; in the SMT case it's
270 // possible that its ITB entry was kicked out.
271 warn("%lli: Instruction PC %s was not found in the "
272 "ITB!", curTick(), thread->pcState());
273 handleError(unverifiedInst);
274
275 // go to the next instruction
276 advancePC(NoFault);
277
278 // Give up on an ITB fault..
279 delete memReq;
280 unverifiedInst = NULL;
281 return;
282 } else {
283 // The instruction is carrying an ITB fault. Handle
284 // the fault and see if our results match the CPU on
285 // the next tick().
286 fault = unverifiedInst->getFault();
287 delete memReq;
288 break;
289 }
290 } else {
291 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
292
293 pkt->dataStatic(&machInst);
294 icachePort->sendFunctional(pkt);
295 machInst = gtoh(machInst);
296
297 delete memReq;
298 delete pkt;
299 }
300 }
301
302 if (fault == NoFault) {
303 TheISA::PCState pcState = thread->pcState();
304
305 if (isRomMicroPC(pcState.microPC())) {
306 fetchDone = true;
307 curStaticInst =
308 microcodeRom.fetchMicroop(pcState.microPC(), NULL);
309 } else if (!curMacroStaticInst) {
310 //We're not in the middle of a macro instruction
311 StaticInstPtr instPtr = NULL;
312
313 //Predecode, ie bundle up an ExtMachInst
314 //If more fetch data is needed, pass it in.
315 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
316 thread->decoder.moreBytes(pcState, fetchPC, machInst);
317
318 //If an instruction is ready, decode it.
319 //Otherwise, we'll have to fetch beyond the
320 //MachInst at the current pc.
321 if (thread->decoder.instReady()) {
322 fetchDone = true;
323 instPtr = thread->decoder.decode(pcState);
324 thread->pcState(pcState);
325 } else {
326 fetchDone = false;
327 fetchOffset += sizeof(TheISA::MachInst);
328 }
329
330 //If we decoded an instruction and it's microcoded,
331 //start pulling out micro ops
332 if (instPtr && instPtr->isMacroop()) {
333 curMacroStaticInst = instPtr;
334 curStaticInst =
335 instPtr->fetchMicroop(pcState.microPC());
336 } else {
337 curStaticInst = instPtr;
338 }
339 } else {
340 // Read the next micro op from the macro-op
341 curStaticInst =
342 curMacroStaticInst->fetchMicroop(pcState.microPC());
343 fetchDone = true;
344 }
345 }
346 }
347 // reset decoder on Checker
348 thread->decoder.reset();
349
350 // Check Checker and CPU get same instruction, and record
351 // any faults the CPU may have had.
352 Fault unverifiedFault;
353 if (fault == NoFault) {
354 unverifiedFault = unverifiedInst->getFault();
355
356 // Checks that the instruction matches what we expected it to be.
357 // Checks both the machine instruction and the PC.
358 validateInst(unverifiedInst);
359 }
360
361 // keep an instruction count
362 numInst++;
363
364
365 // Either the instruction was a fault and we should process the fault,
366 // or we should just go ahead execute the instruction. This assumes
367 // that the instruction is properly marked as a fault.
368 if (fault == NoFault) {
369 // Execute Checker instruction and trace
370 if (!unverifiedInst->isUnverifiable()) {
371 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
372 tc,
373 curStaticInst,
374 pcState(),
375 curMacroStaticInst);
376 fault = curStaticInst->execute(this, traceData);
377 if (traceData) {
378 traceData->dump();
379 delete traceData;
380 }
381 }
382
383 if (fault == NoFault && unverifiedFault == NoFault) {
384 thread->funcExeInst++;
385 // Checks to make sure instrution results are correct.
386 validateExecution(unverifiedInst);
387
388 if (curStaticInst->isLoad()) {
389 ++numLoad;
390 }
391 } else if (fault != NoFault && unverifiedFault == NoFault) {
392 panic("%lli: sn: %lli at PC: %s took a fault in checker "
393 "but not in driver CPU\n", curTick(),
394 unverifiedInst->seqNum, unverifiedInst->pcState());
395 } else if (fault == NoFault && unverifiedFault != NoFault) {
396 panic("%lli: sn: %lli at PC: %s took a fault in driver "
397 "CPU but not in checker\n", curTick(),
398 unverifiedInst->seqNum, unverifiedInst->pcState());
399 }
400 }
401
402 // Take any faults here
403 if (fault != NoFault) {
404 if (FullSystem) {
405 fault->invoke(tc, curStaticInst);
406 willChangePC = true;
407 newPCState = thread->pcState();
408 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
409 curMacroStaticInst = StaticInst::nullStaticInstPtr;
410 }
411 } else {
412 advancePC(fault);
413 }
414
415 if (FullSystem) {
416 // @todo: Determine if these should happen only if the
417 // instruction hasn't faulted. In the SimpleCPU case this may
418 // not be true, but in the O3 or Ozone case this may be true.
419 Addr oldpc;
420 int count = 0;
421 do {
422 oldpc = thread->instAddr();
423 system->pcEventQueue.service(tc);
424 count++;
425 } while (oldpc != thread->instAddr());
426 if (count > 1) {
427 willChangePC = true;
428 newPCState = thread->pcState();
429 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
430 }
431 }
432
433 // @todo: Optionally can check all registers. (Or just those
434 // that have been modified).
435 validateState();
436
437 // Continue verifying instructions if there's another completed
438 // instruction waiting to be verified.
439 if (instList.empty()) {
440 break;
441 } else if (instList.front()->isCompleted()) {
442 unverifiedInst = NULL;
443 unverifiedInst = instList.front();
444 instList.pop_front();
445 } else {
446 break;
447 }
448 }
449 unverifiedInst = NULL;
450}
451
452template <class Impl>
453void
454Checker<Impl>::switchOut()
455{
456 instList.clear();
457}
458
459template <class Impl>
460void
461Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
462{
463}
464
465template <class Impl>
466void
467Checker<Impl>::validateInst(DynInstPtr &inst)
468{
469 if (inst->instAddr() != thread->instAddr()) {
470 warn("%lli: PCs do not match! Inst: %s, checker: %s",
471 curTick(), inst->pcState(), thread->pcState());
472 if (changedPC) {
473 warn("%lli: Changed PCs recently, may not be an error",
474 curTick());
475 } else {
476 handleError(inst);
477 }
478 }
479
480 if (curStaticInst != inst->staticInst) {
481 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
482 curStaticInst->getName(), inst->staticInst->getName());
483 }
484}
485
486template <class Impl>
487void
488Checker<Impl>::validateExecution(DynInstPtr &inst)
489{
490 uint64_t checker_val;
491 uint64_t inst_val;
492 int idx = -1;
493 bool result_mismatch = false;
494
495 if (inst->isUnverifiable()) {
496 // Unverifiable instructions assume they were executed
497 // properly by the CPU. Grab the result from the
498 // instruction and write it to the register.
499 copyResult(inst, 0, idx);
500 } else if (inst->numDestRegs() > 0 && !result.empty()) {
501 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
502 inst->numDestRegs(), result.size());
503 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
504 result.front().get(checker_val);
505 result.pop();
506 inst_val = 0;
507 inst->template popResult<uint64_t>(inst_val);
508 if (checker_val != inst_val) {
509 result_mismatch = true;
510 idx = i;
511 break;
512 }
513 }
514 } // Checker CPU checks all the saved results in the dyninst passed by
515 // the cpu model being checked against the saved results present in
516 // the static inst executed in the Checker. Sometimes the number
517 // of saved results differs between the dyninst and static inst, but
518 // this is ok and not a bug. May be worthwhile to try and correct this.
519
520 if (result_mismatch) {
521 warn("%lli: Instruction results do not match! (Values may not "
522 "actually be integers) Inst: %#x, checker: %#x",
523 curTick(), inst_val, checker_val);
524
525 // It's useful to verify load values from memory, but in MP
526 // systems the value obtained at execute may be different than
527 // the value obtained at completion. Similarly DMA can
528 // present the same problem on even UP systems. Thus there is
529 // the option to only warn on loads having a result error.
530 // The load/store queue in Detailed CPU can also cause problems
531 // if load/store forwarding is allowed.
532 if (inst->isLoad() && warnOnlyOnLoadError) {
533 copyResult(inst, inst_val, idx);
534 } else {
535 handleError(inst);
536 }
537 }
538
539 if (inst->nextInstAddr() != thread->nextInstAddr()) {
540 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
541 "checker: %#x",
542 curTick(), inst->nextInstAddr(), thread->nextInstAddr());
543 handleError(inst);
544 }
545
546 // Checking side effect registers can be difficult if they are not
547 // checked simultaneously with the execution of the instruction.
548 // This is because other valid instructions may have modified
549 // these registers in the meantime, and their values are not
550 // stored within the DynInst.
551 while (!miscRegIdxs.empty()) {
552 int misc_reg_idx = miscRegIdxs.front();
553 miscRegIdxs.pop();
554
555 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
556 thread->readMiscRegNoEffect(misc_reg_idx)) {
557 warn("%lli: Misc reg idx %i (side effect) does not match! "
558 "Inst: %#x, checker: %#x",
559 curTick(), misc_reg_idx,
560 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
561 thread->readMiscRegNoEffect(misc_reg_idx));
562 handleError(inst);
563 }
564 }
565}
566
567
568// This function is weird, if it is called it means the Checker and
569// O3 have diverged, so panic is called for now. It may be useful
570// to resynch states and continue if the divergence is a false positive
571template <class Impl>
572void
573Checker<Impl>::validateState()
574{
575 if (updateThisCycle) {
576 // Change this back to warn if divergences end up being false positives
577 panic("%lli: Instruction PC %#x results didn't match up, copying all "
578 "registers from main CPU", curTick(), unverifiedInst->instAddr());
579
580 // Terribly convoluted way to make sure O3 model does not implode
581 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
582 unverifiedInst->thread->noSquashFromTC = true;
583
584 // Heavy-weight copying of all registers
585 thread->copyArchRegs(unverifiedInst->tcBase());
586 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
587
588 // Set curStaticInst to unverifiedInst->staticInst
589 curStaticInst = unverifiedInst->staticInst;
590 // Also advance the PC. Hopefully no PC-based events happened.
591 advancePC(NoFault);
592 updateThisCycle = false;
593 }
594}
595
596template <class Impl>
597void
598Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
599 int start_idx)
600{
601 // We've already popped one dest off the queue,
602 // so do the fix-up then start with the next dest reg;
603 if (start_idx >= 0) {
604 RegIndex idx = inst->destRegIdx(start_idx);
605 switch (regIdxToClass(idx)) {
606 case IntRegClass:
607 thread->setIntReg(idx, mismatch_val);
608 break;
609 case FloatRegClass:
610 thread->setFloatRegBits(idx, mismatch_val);
611 break;
612 case CCRegClass:
613 thread->setCCReg(idx, mismatch_val);
614 break;
615 case MiscRegClass:
616 thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
617 mismatch_val);
618 break;
619 }
620 }
621 start_idx++;
622 uint64_t res = 0;
623 for (int i = start_idx; i < inst->numDestRegs(); i++) {
624 RegIndex idx = inst->destRegIdx(i);
625 inst->template popResult<uint64_t>(res);
626 switch (regIdxToClass(idx)) {
627 case IntRegClass:
628 thread->setIntReg(idx, res);
629 break;
630 case FloatRegClass:
631 thread->setFloatRegBits(idx, res);
632 break;
633 case CCRegClass:
634 thread->setCCReg(idx, res);
635 break;
636 case MiscRegClass:
637 // Try to get the proper misc register index for ARM here...
638 thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
639 break;
640 // else Register is out of range...
641 }
642 }
643}
644
645template <class Impl>
646void
647Checker<Impl>::dumpAndExit(DynInstPtr &inst)
648{
649 cprintf("Error detected, instruction information:\n");
650 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
651 "Completed:%i\n",
652 inst->pcState(),
653 inst->nextInstAddr(),
654 inst->seqNum,
655 inst->threadNumber,
656 inst->isCompleted());
657 inst->dump();
658 CheckerCPU::dumpAndExit();
659}
660
661template <class Impl>
662void
663Checker<Impl>::dumpInsts()
664{
665 int num = 0;
666
667 InstListIt inst_list_it = --(instList.end());
668
669 cprintf("Inst list size: %i\n", instList.size());
670
671 while (inst_list_it != instList.end())
672 {
673 cprintf("Instruction:%i\n",
674 num);
675
676 cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n"
677 "Completed:%i\n",
678 (*inst_list_it)->pcState(),
679 (*inst_list_it)->seqNum,
680 (*inst_list_it)->threadNumber,
681 (*inst_list_it)->isCompleted());
682
683 cprintf("\n");
684
685 inst_list_it--;
686 ++num;
687 }
688
689}
|