3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/isa_traits.hh"
48#include "arch/vtophys.hh"
49#include "base/refcnt.hh"
50#include "config/the_isa.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/exetrace.hh"
| 4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Geoffrey Blake
43 */
44
45#include <list>
46#include <string>
47
48#include "arch/isa_traits.hh"
49#include "arch/vtophys.hh"
50#include "base/refcnt.hh"
51#include "config/the_isa.hh"
52#include "cpu/base_dyn_inst.hh"
53#include "cpu/exetrace.hh"
|
53#include "cpu/simple_thread.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56#include "cpu/checker/cpu.hh"
57#include "debug/Checker.hh"
58#include "sim/full_system.hh"
59#include "sim/sim_object.hh"
60#include "sim/stats.hh"
61
62using namespace std;
63using namespace TheISA;
64
65template <class Impl>
66void
67Checker<Impl>::advancePC(Fault fault)
68{
69 if (fault != NoFault) {
70 curMacroStaticInst = StaticInst::nullStaticInstPtr;
71 fault->invoke(tc, curStaticInst);
72 thread->decoder.reset();
73 } else {
74 if (curStaticInst) {
75 if (curStaticInst->isLastMicroop())
76 curMacroStaticInst = StaticInst::nullStaticInstPtr;
77 TheISA::PCState pcState = thread->pcState();
78 TheISA::advancePC(pcState, curStaticInst);
79 thread->pcState(pcState);
80 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
81 }
82 }
83}
84//////////////////////////////////////////////////
85
86template <class Impl>
87void
88Checker<Impl>::handlePendingInt()
89{
90 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
91 thread->pcState(), instList.size());
92 DynInstPtr boundaryInst = NULL;
93 if (!instList.empty()) {
94 // Set the instructions as completed and verify as much as possible.
95 DynInstPtr inst;
96 typename std::list<DynInstPtr>::iterator itr;
97
98 for (itr = instList.begin(); itr != instList.end(); itr++) {
99 (*itr)->setCompleted();
100 }
101
102 inst = instList.front();
103 boundaryInst = instList.back();
104 verify(inst); // verify the instructions
105 inst = NULL;
106 }
107 if ((!boundaryInst && curMacroStaticInst &&
108 curStaticInst->isDelayedCommit() &&
109 !curStaticInst->isLastMicroop()) ||
110 (boundaryInst && boundaryInst->isDelayedCommit() &&
111 !boundaryInst->isLastMicroop())) {
112 panic("%lli: Trying to take an interrupt in middle of "
113 "a non-interuptable instruction!", curTick());
114 }
115 boundaryInst = NULL;
116 thread->decoder.reset();
117 curMacroStaticInst = StaticInst::nullStaticInstPtr;
118}
119
120template <class Impl>
121void
122Checker<Impl>::verify(DynInstPtr &completed_inst)
123{
124 DynInstPtr inst;
125
126 // Make sure serializing instructions are actually
127 // seen as serializing to commit. instList should be
128 // empty in these cases.
129 if ((completed_inst->isSerializing() ||
130 completed_inst->isSerializeBefore()) &&
131 (!instList.empty() ?
132 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
133 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
134 " entering instList with other instructions\n", curTick(),
135 completed_inst->seqNum, completed_inst->pcState());
136 }
137
138 // Either check this instruction, or add it to a list of
139 // instructions waiting to be checked. Instructions must be
140 // checked in program order, so if a store has committed yet not
141 // completed, there may be some instructions that are waiting
142 // behind it that have completed and must be checked.
143 if (!instList.empty()) {
144 if (youngestSN < completed_inst->seqNum) {
145 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
146 completed_inst->seqNum, completed_inst->pcState());
147 instList.push_back(completed_inst);
148 youngestSN = completed_inst->seqNum;
149 }
150
151 if (!instList.front()->isCompleted()) {
152 return;
153 } else {
154 inst = instList.front();
155 instList.pop_front();
156 }
157 } else {
158 if (!completed_inst->isCompleted()) {
159 if (youngestSN < completed_inst->seqNum) {
160 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
161 completed_inst->seqNum, completed_inst->pcState());
162 instList.push_back(completed_inst);
163 youngestSN = completed_inst->seqNum;
164 }
165 return;
166 } else {
167 if (youngestSN < completed_inst->seqNum) {
168 inst = completed_inst;
169 youngestSN = completed_inst->seqNum;
170 } else {
171 return;
172 }
173 }
174 }
175
176 // Make sure a serializing instruction is actually seen as
177 // serializing. instList should be empty here
178 if (inst->isSerializeAfter() && !instList.empty()) {
179 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
180 " exiting instList with other instructions\n", curTick(),
181 completed_inst->seqNum, completed_inst->pcState());
182 }
183 unverifiedInst = inst;
184 inst = NULL;
185
186 // Try to check all instructions that are completed, ending if we
187 // run out of instructions to check or if an instruction is not
188 // yet completed.
189 while (1) {
190 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
191 unverifiedInst->seqNum, unverifiedInst->pcState());
192 unverifiedReq = NULL;
193 unverifiedReq = unverifiedInst->reqToVerify;
194 unverifiedMemData = unverifiedInst->memData;
195 // Make sure results queue is empty
196 while (!result.empty()) {
197 result.pop();
198 }
199 numCycles++;
200
201 Fault fault = NoFault;
202
203 // maintain $r0 semantics
204 thread->setIntReg(ZeroReg, 0);
205#if THE_ISA == ALPHA_ISA
206 thread->setFloatReg(ZeroReg, 0.0);
207#endif
208
209 // Check if any recent PC changes match up with anything we
210 // expect to happen. This is mostly to check if traps or
211 // PC-based events have occurred in both the checker and CPU.
212 if (changedPC) {
213 DPRINTF(Checker, "Changed PC recently to %s\n",
214 thread->pcState());
215 if (willChangePC) {
216 if (newPCState == thread->pcState()) {
217 DPRINTF(Checker, "Changed PC matches expected PC\n");
218 } else {
219 warn("%lli: Changed PC does not match expected PC, "
220 "changed: %s, expected: %s",
221 curTick(), thread->pcState(), newPCState);
222 CheckerCPU::handleError();
223 }
224 willChangePC = false;
225 }
226 changedPC = false;
227 }
228 if (changedNextPC) {
229 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
230 thread->nextInstAddr());
231 changedNextPC = false;
232 }
233
234 // Try to fetch the instruction
235 uint64_t fetchOffset = 0;
236 bool fetchDone = false;
237
238 while (!fetchDone) {
239 Addr fetch_PC = thread->instAddr();
240 fetch_PC = (fetch_PC & PCMask) + fetchOffset;
241
242 MachInst machInst;
243
244 // If not in the middle of a macro instruction
245 if (!curMacroStaticInst) {
246 // set up memory request for instruction fetch
247 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
248 sizeof(MachInst),
249 0,
250 masterId,
251 fetch_PC, thread->contextId(),
252 unverifiedInst->threadNumber);
253 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
254 Request::INST_FETCH, masterId, thread->instAddr());
255
256
257 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
258
259 if (fault != NoFault) {
260 if (unverifiedInst->getFault() == NoFault) {
261 // In this case the instruction was not a dummy
262 // instruction carrying an ITB fault. In the single
263 // threaded case the ITB should still be able to
264 // translate this instruction; in the SMT case it's
265 // possible that its ITB entry was kicked out.
266 warn("%lli: Instruction PC %s was not found in the "
267 "ITB!", curTick(), thread->pcState());
268 handleError(unverifiedInst);
269
270 // go to the next instruction
271 advancePC(NoFault);
272
273 // Give up on an ITB fault..
274 delete memReq;
275 unverifiedInst = NULL;
276 return;
277 } else {
278 // The instruction is carrying an ITB fault. Handle
279 // the fault and see if our results match the CPU on
280 // the next tick().
281 fault = unverifiedInst->getFault();
282 delete memReq;
283 break;
284 }
285 } else {
286 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
287
288 pkt->dataStatic(&machInst);
289 icachePort->sendFunctional(pkt);
290 machInst = gtoh(machInst);
291
292 delete memReq;
293 delete pkt;
294 }
295 }
296
297 if (fault == NoFault) {
298 TheISA::PCState pcState = thread->pcState();
299
300 if (isRomMicroPC(pcState.microPC())) {
301 fetchDone = true;
302 curStaticInst =
303 microcodeRom.fetchMicroop(pcState.microPC(), NULL);
304 } else if (!curMacroStaticInst) {
305 //We're not in the middle of a macro instruction
306 StaticInstPtr instPtr = NULL;
307
308 //Predecode, ie bundle up an ExtMachInst
309 //If more fetch data is needed, pass it in.
310 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
311 thread->decoder.moreBytes(pcState, fetchPC, machInst);
312
313 //If an instruction is ready, decode it.
314 //Otherwise, we'll have to fetch beyond the
315 //MachInst at the current pc.
316 if (thread->decoder.instReady()) {
317 fetchDone = true;
318 instPtr = thread->decoder.decode(pcState);
319 thread->pcState(pcState);
320 } else {
321 fetchDone = false;
322 fetchOffset += sizeof(TheISA::MachInst);
323 }
324
325 //If we decoded an instruction and it's microcoded,
326 //start pulling out micro ops
327 if (instPtr && instPtr->isMacroop()) {
328 curMacroStaticInst = instPtr;
329 curStaticInst =
330 instPtr->fetchMicroop(pcState.microPC());
331 } else {
332 curStaticInst = instPtr;
333 }
334 } else {
335 // Read the next micro op from the macro-op
336 curStaticInst =
337 curMacroStaticInst->fetchMicroop(pcState.microPC());
338 fetchDone = true;
339 }
340 }
341 }
342 // reset decoder on Checker
343 thread->decoder.reset();
344
345 // Check Checker and CPU get same instruction, and record
346 // any faults the CPU may have had.
347 Fault unverifiedFault;
348 if (fault == NoFault) {
349 unverifiedFault = unverifiedInst->getFault();
350
351 // Checks that the instruction matches what we expected it to be.
352 // Checks both the machine instruction and the PC.
353 validateInst(unverifiedInst);
354 }
355
356 // keep an instruction count
357 numInst++;
358
359
360 // Either the instruction was a fault and we should process the fault,
361 // or we should just go ahead execute the instruction. This assumes
362 // that the instruction is properly marked as a fault.
363 if (fault == NoFault) {
364 // Execute Checker instruction and trace
365 if (!unverifiedInst->isUnverifiable()) {
366 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
367 tc,
368 curStaticInst,
369 pcState(),
370 curMacroStaticInst);
371 fault = curStaticInst->execute(this, traceData);
372 if (traceData) {
373 traceData->dump();
374 delete traceData;
375 }
376 }
377
378 if (fault == NoFault && unverifiedFault == NoFault) {
379 thread->funcExeInst++;
380 // Checks to make sure instrution results are correct.
381 validateExecution(unverifiedInst);
382
383 if (curStaticInst->isLoad()) {
384 ++numLoad;
385 }
386 } else if (fault != NoFault && unverifiedFault == NoFault) {
387 panic("%lli: sn: %lli at PC: %s took a fault in checker "
388 "but not in driver CPU\n", curTick(),
389 unverifiedInst->seqNum, unverifiedInst->pcState());
390 } else if (fault == NoFault && unverifiedFault != NoFault) {
391 panic("%lli: sn: %lli at PC: %s took a fault in driver "
392 "CPU but not in checker\n", curTick(),
393 unverifiedInst->seqNum, unverifiedInst->pcState());
394 }
395 }
396
397 // Take any faults here
398 if (fault != NoFault) {
399 if (FullSystem) {
400 fault->invoke(tc, curStaticInst);
401 willChangePC = true;
402 newPCState = thread->pcState();
403 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
404 curMacroStaticInst = StaticInst::nullStaticInstPtr;
405 }
406 } else {
407 advancePC(fault);
408 }
409
410 if (FullSystem) {
411 // @todo: Determine if these should happen only if the
412 // instruction hasn't faulted. In the SimpleCPU case this may
413 // not be true, but in the O3 or Ozone case this may be true.
414 Addr oldpc;
415 int count = 0;
416 do {
417 oldpc = thread->instAddr();
418 system->pcEventQueue.service(tc);
419 count++;
420 } while (oldpc != thread->instAddr());
421 if (count > 1) {
422 willChangePC = true;
423 newPCState = thread->pcState();
424 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
425 }
426 }
427
428 // @todo: Optionally can check all registers. (Or just those
429 // that have been modified).
430 validateState();
431
432 // Continue verifying instructions if there's another completed
433 // instruction waiting to be verified.
434 if (instList.empty()) {
435 break;
436 } else if (instList.front()->isCompleted()) {
437 unverifiedInst = NULL;
438 unverifiedInst = instList.front();
439 instList.pop_front();
440 } else {
441 break;
442 }
443 }
444 unverifiedInst = NULL;
445}
446
447template <class Impl>
448void
449Checker<Impl>::switchOut()
450{
451 instList.clear();
452}
453
454template <class Impl>
455void
456Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
457{
458}
459
460template <class Impl>
461void
462Checker<Impl>::validateInst(DynInstPtr &inst)
463{
464 if (inst->instAddr() != thread->instAddr()) {
465 warn("%lli: PCs do not match! Inst: %s, checker: %s",
466 curTick(), inst->pcState(), thread->pcState());
467 if (changedPC) {
468 warn("%lli: Changed PCs recently, may not be an error",
469 curTick());
470 } else {
471 handleError(inst);
472 }
473 }
474
475 if (curStaticInst != inst->staticInst) {
476 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
477 curStaticInst->getName(), inst->staticInst->getName());
478 }
479}
480
481template <class Impl>
482void
483Checker<Impl>::validateExecution(DynInstPtr &inst)
484{
485 uint64_t checker_val;
486 uint64_t inst_val;
487 int idx = -1;
488 bool result_mismatch = false;
489
490 if (inst->isUnverifiable()) {
491 // Unverifiable instructions assume they were executed
492 // properly by the CPU. Grab the result from the
493 // instruction and write it to the register.
494 copyResult(inst, 0, idx);
495 } else if (inst->numDestRegs() > 0 && !result.empty()) {
496 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
497 inst->numDestRegs(), result.size());
498 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
499 result.front().get(checker_val);
500 result.pop();
501 inst_val = 0;
502 inst->template popResult<uint64_t>(inst_val);
503 if (checker_val != inst_val) {
504 result_mismatch = true;
505 idx = i;
506 break;
507 }
508 }
509 } // Checker CPU checks all the saved results in the dyninst passed by
510 // the cpu model being checked against the saved results present in
511 // the static inst executed in the Checker. Sometimes the number
512 // of saved results differs between the dyninst and static inst, but
513 // this is ok and not a bug. May be worthwhile to try and correct this.
514
515 if (result_mismatch) {
516 warn("%lli: Instruction results do not match! (Values may not "
517 "actually be integers) Inst: %#x, checker: %#x",
518 curTick(), inst_val, checker_val);
519
520 // It's useful to verify load values from memory, but in MP
521 // systems the value obtained at execute may be different than
522 // the value obtained at completion. Similarly DMA can
523 // present the same problem on even UP systems. Thus there is
524 // the option to only warn on loads having a result error.
525 // The load/store queue in Detailed CPU can also cause problems
526 // if load/store forwarding is allowed.
527 if (inst->isLoad() && warnOnlyOnLoadError) {
528 copyResult(inst, inst_val, idx);
529 } else {
530 handleError(inst);
531 }
532 }
533
534 if (inst->nextInstAddr() != thread->nextInstAddr()) {
535 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
536 "checker: %#x",
537 curTick(), inst->nextInstAddr(), thread->nextInstAddr());
538 handleError(inst);
539 }
540
541 // Checking side effect registers can be difficult if they are not
542 // checked simultaneously with the execution of the instruction.
543 // This is because other valid instructions may have modified
544 // these registers in the meantime, and their values are not
545 // stored within the DynInst.
546 while (!miscRegIdxs.empty()) {
547 int misc_reg_idx = miscRegIdxs.front();
548 miscRegIdxs.pop();
549
550 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
551 thread->readMiscRegNoEffect(misc_reg_idx)) {
552 warn("%lli: Misc reg idx %i (side effect) does not match! "
553 "Inst: %#x, checker: %#x",
554 curTick(), misc_reg_idx,
555 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
556 thread->readMiscRegNoEffect(misc_reg_idx));
557 handleError(inst);
558 }
559 }
560}
561
562
563// This function is weird, if it is called it means the Checker and
564// O3 have diverged, so panic is called for now. It may be useful
565// to resynch states and continue if the divergence is a false positive
566template <class Impl>
567void
568Checker<Impl>::validateState()
569{
570 if (updateThisCycle) {
571 // Change this back to warn if divergences end up being false positives
572 panic("%lli: Instruction PC %#x results didn't match up, copying all "
573 "registers from main CPU", curTick(), unverifiedInst->instAddr());
574
575 // Terribly convoluted way to make sure O3 model does not implode
576 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
577 unverifiedInst->thread->noSquashFromTC = true;
578
579 // Heavy-weight copying of all registers
580 thread->copyArchRegs(unverifiedInst->tcBase());
581 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
582
583 // Set curStaticInst to unverifiedInst->staticInst
584 curStaticInst = unverifiedInst->staticInst;
585 // Also advance the PC. Hopefully no PC-based events happened.
586 advancePC(NoFault);
587 updateThisCycle = false;
588 }
589}
590
591template <class Impl>
592void
593Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
594 int start_idx)
595{
596 // We've already popped one dest off the queue,
597 // so do the fix-up then start with the next dest reg;
598 if (start_idx >= 0) {
599 RegIndex idx = inst->destRegIdx(start_idx);
| 55#include "cpu/simple_thread.hh"
56#include "cpu/static_inst.hh"
57#include "cpu/thread_context.hh"
58#include "cpu/checker/cpu.hh"
59#include "debug/Checker.hh"
60#include "sim/full_system.hh"
61#include "sim/sim_object.hh"
62#include "sim/stats.hh"
63
64using namespace std;
65using namespace TheISA;
66
67template <class Impl>
68void
69Checker<Impl>::advancePC(Fault fault)
70{
71 if (fault != NoFault) {
72 curMacroStaticInst = StaticInst::nullStaticInstPtr;
73 fault->invoke(tc, curStaticInst);
74 thread->decoder.reset();
75 } else {
76 if (curStaticInst) {
77 if (curStaticInst->isLastMicroop())
78 curMacroStaticInst = StaticInst::nullStaticInstPtr;
79 TheISA::PCState pcState = thread->pcState();
80 TheISA::advancePC(pcState, curStaticInst);
81 thread->pcState(pcState);
82 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState());
83 }
84 }
85}
86//////////////////////////////////////////////////
87
88template <class Impl>
89void
90Checker<Impl>::handlePendingInt()
91{
92 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n",
93 thread->pcState(), instList.size());
94 DynInstPtr boundaryInst = NULL;
95 if (!instList.empty()) {
96 // Set the instructions as completed and verify as much as possible.
97 DynInstPtr inst;
98 typename std::list<DynInstPtr>::iterator itr;
99
100 for (itr = instList.begin(); itr != instList.end(); itr++) {
101 (*itr)->setCompleted();
102 }
103
104 inst = instList.front();
105 boundaryInst = instList.back();
106 verify(inst); // verify the instructions
107 inst = NULL;
108 }
109 if ((!boundaryInst && curMacroStaticInst &&
110 curStaticInst->isDelayedCommit() &&
111 !curStaticInst->isLastMicroop()) ||
112 (boundaryInst && boundaryInst->isDelayedCommit() &&
113 !boundaryInst->isLastMicroop())) {
114 panic("%lli: Trying to take an interrupt in middle of "
115 "a non-interuptable instruction!", curTick());
116 }
117 boundaryInst = NULL;
118 thread->decoder.reset();
119 curMacroStaticInst = StaticInst::nullStaticInstPtr;
120}
121
122template <class Impl>
123void
124Checker<Impl>::verify(DynInstPtr &completed_inst)
125{
126 DynInstPtr inst;
127
128 // Make sure serializing instructions are actually
129 // seen as serializing to commit. instList should be
130 // empty in these cases.
131 if ((completed_inst->isSerializing() ||
132 completed_inst->isSerializeBefore()) &&
133 (!instList.empty() ?
134 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
135 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is"
136 " entering instList with other instructions\n", curTick(),
137 completed_inst->seqNum, completed_inst->pcState());
138 }
139
140 // Either check this instruction, or add it to a list of
141 // instructions waiting to be checked. Instructions must be
142 // checked in program order, so if a store has committed yet not
143 // completed, there may be some instructions that are waiting
144 // behind it that have completed and must be checked.
145 if (!instList.empty()) {
146 if (youngestSN < completed_inst->seqNum) {
147 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
148 completed_inst->seqNum, completed_inst->pcState());
149 instList.push_back(completed_inst);
150 youngestSN = completed_inst->seqNum;
151 }
152
153 if (!instList.front()->isCompleted()) {
154 return;
155 } else {
156 inst = instList.front();
157 instList.pop_front();
158 }
159 } else {
160 if (!completed_inst->isCompleted()) {
161 if (youngestSN < completed_inst->seqNum) {
162 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n",
163 completed_inst->seqNum, completed_inst->pcState());
164 instList.push_back(completed_inst);
165 youngestSN = completed_inst->seqNum;
166 }
167 return;
168 } else {
169 if (youngestSN < completed_inst->seqNum) {
170 inst = completed_inst;
171 youngestSN = completed_inst->seqNum;
172 } else {
173 return;
174 }
175 }
176 }
177
178 // Make sure a serializing instruction is actually seen as
179 // serializing. instList should be empty here
180 if (inst->isSerializeAfter() && !instList.empty()) {
181 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is"
182 " exiting instList with other instructions\n", curTick(),
183 completed_inst->seqNum, completed_inst->pcState());
184 }
185 unverifiedInst = inst;
186 inst = NULL;
187
188 // Try to check all instructions that are completed, ending if we
189 // run out of instructions to check or if an instruction is not
190 // yet completed.
191 while (1) {
192 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n",
193 unverifiedInst->seqNum, unverifiedInst->pcState());
194 unverifiedReq = NULL;
195 unverifiedReq = unverifiedInst->reqToVerify;
196 unverifiedMemData = unverifiedInst->memData;
197 // Make sure results queue is empty
198 while (!result.empty()) {
199 result.pop();
200 }
201 numCycles++;
202
203 Fault fault = NoFault;
204
205 // maintain $r0 semantics
206 thread->setIntReg(ZeroReg, 0);
207#if THE_ISA == ALPHA_ISA
208 thread->setFloatReg(ZeroReg, 0.0);
209#endif
210
211 // Check if any recent PC changes match up with anything we
212 // expect to happen. This is mostly to check if traps or
213 // PC-based events have occurred in both the checker and CPU.
214 if (changedPC) {
215 DPRINTF(Checker, "Changed PC recently to %s\n",
216 thread->pcState());
217 if (willChangePC) {
218 if (newPCState == thread->pcState()) {
219 DPRINTF(Checker, "Changed PC matches expected PC\n");
220 } else {
221 warn("%lli: Changed PC does not match expected PC, "
222 "changed: %s, expected: %s",
223 curTick(), thread->pcState(), newPCState);
224 CheckerCPU::handleError();
225 }
226 willChangePC = false;
227 }
228 changedPC = false;
229 }
230 if (changedNextPC) {
231 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
232 thread->nextInstAddr());
233 changedNextPC = false;
234 }
235
236 // Try to fetch the instruction
237 uint64_t fetchOffset = 0;
238 bool fetchDone = false;
239
240 while (!fetchDone) {
241 Addr fetch_PC = thread->instAddr();
242 fetch_PC = (fetch_PC & PCMask) + fetchOffset;
243
244 MachInst machInst;
245
246 // If not in the middle of a macro instruction
247 if (!curMacroStaticInst) {
248 // set up memory request for instruction fetch
249 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
250 sizeof(MachInst),
251 0,
252 masterId,
253 fetch_PC, thread->contextId(),
254 unverifiedInst->threadNumber);
255 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
256 Request::INST_FETCH, masterId, thread->instAddr());
257
258
259 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
260
261 if (fault != NoFault) {
262 if (unverifiedInst->getFault() == NoFault) {
263 // In this case the instruction was not a dummy
264 // instruction carrying an ITB fault. In the single
265 // threaded case the ITB should still be able to
266 // translate this instruction; in the SMT case it's
267 // possible that its ITB entry was kicked out.
268 warn("%lli: Instruction PC %s was not found in the "
269 "ITB!", curTick(), thread->pcState());
270 handleError(unverifiedInst);
271
272 // go to the next instruction
273 advancePC(NoFault);
274
275 // Give up on an ITB fault..
276 delete memReq;
277 unverifiedInst = NULL;
278 return;
279 } else {
280 // The instruction is carrying an ITB fault. Handle
281 // the fault and see if our results match the CPU on
282 // the next tick().
283 fault = unverifiedInst->getFault();
284 delete memReq;
285 break;
286 }
287 } else {
288 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
289
290 pkt->dataStatic(&machInst);
291 icachePort->sendFunctional(pkt);
292 machInst = gtoh(machInst);
293
294 delete memReq;
295 delete pkt;
296 }
297 }
298
299 if (fault == NoFault) {
300 TheISA::PCState pcState = thread->pcState();
301
302 if (isRomMicroPC(pcState.microPC())) {
303 fetchDone = true;
304 curStaticInst =
305 microcodeRom.fetchMicroop(pcState.microPC(), NULL);
306 } else if (!curMacroStaticInst) {
307 //We're not in the middle of a macro instruction
308 StaticInstPtr instPtr = NULL;
309
310 //Predecode, ie bundle up an ExtMachInst
311 //If more fetch data is needed, pass it in.
312 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
313 thread->decoder.moreBytes(pcState, fetchPC, machInst);
314
315 //If an instruction is ready, decode it.
316 //Otherwise, we'll have to fetch beyond the
317 //MachInst at the current pc.
318 if (thread->decoder.instReady()) {
319 fetchDone = true;
320 instPtr = thread->decoder.decode(pcState);
321 thread->pcState(pcState);
322 } else {
323 fetchDone = false;
324 fetchOffset += sizeof(TheISA::MachInst);
325 }
326
327 //If we decoded an instruction and it's microcoded,
328 //start pulling out micro ops
329 if (instPtr && instPtr->isMacroop()) {
330 curMacroStaticInst = instPtr;
331 curStaticInst =
332 instPtr->fetchMicroop(pcState.microPC());
333 } else {
334 curStaticInst = instPtr;
335 }
336 } else {
337 // Read the next micro op from the macro-op
338 curStaticInst =
339 curMacroStaticInst->fetchMicroop(pcState.microPC());
340 fetchDone = true;
341 }
342 }
343 }
344 // reset decoder on Checker
345 thread->decoder.reset();
346
347 // Check Checker and CPU get same instruction, and record
348 // any faults the CPU may have had.
349 Fault unverifiedFault;
350 if (fault == NoFault) {
351 unverifiedFault = unverifiedInst->getFault();
352
353 // Checks that the instruction matches what we expected it to be.
354 // Checks both the machine instruction and the PC.
355 validateInst(unverifiedInst);
356 }
357
358 // keep an instruction count
359 numInst++;
360
361
362 // Either the instruction was a fault and we should process the fault,
363 // or we should just go ahead execute the instruction. This assumes
364 // that the instruction is properly marked as a fault.
365 if (fault == NoFault) {
366 // Execute Checker instruction and trace
367 if (!unverifiedInst->isUnverifiable()) {
368 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
369 tc,
370 curStaticInst,
371 pcState(),
372 curMacroStaticInst);
373 fault = curStaticInst->execute(this, traceData);
374 if (traceData) {
375 traceData->dump();
376 delete traceData;
377 }
378 }
379
380 if (fault == NoFault && unverifiedFault == NoFault) {
381 thread->funcExeInst++;
382 // Checks to make sure instrution results are correct.
383 validateExecution(unverifiedInst);
384
385 if (curStaticInst->isLoad()) {
386 ++numLoad;
387 }
388 } else if (fault != NoFault && unverifiedFault == NoFault) {
389 panic("%lli: sn: %lli at PC: %s took a fault in checker "
390 "but not in driver CPU\n", curTick(),
391 unverifiedInst->seqNum, unverifiedInst->pcState());
392 } else if (fault == NoFault && unverifiedFault != NoFault) {
393 panic("%lli: sn: %lli at PC: %s took a fault in driver "
394 "CPU but not in checker\n", curTick(),
395 unverifiedInst->seqNum, unverifiedInst->pcState());
396 }
397 }
398
399 // Take any faults here
400 if (fault != NoFault) {
401 if (FullSystem) {
402 fault->invoke(tc, curStaticInst);
403 willChangePC = true;
404 newPCState = thread->pcState();
405 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
406 curMacroStaticInst = StaticInst::nullStaticInstPtr;
407 }
408 } else {
409 advancePC(fault);
410 }
411
412 if (FullSystem) {
413 // @todo: Determine if these should happen only if the
414 // instruction hasn't faulted. In the SimpleCPU case this may
415 // not be true, but in the O3 or Ozone case this may be true.
416 Addr oldpc;
417 int count = 0;
418 do {
419 oldpc = thread->instAddr();
420 system->pcEventQueue.service(tc);
421 count++;
422 } while (oldpc != thread->instAddr());
423 if (count > 1) {
424 willChangePC = true;
425 newPCState = thread->pcState();
426 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState);
427 }
428 }
429
430 // @todo: Optionally can check all registers. (Or just those
431 // that have been modified).
432 validateState();
433
434 // Continue verifying instructions if there's another completed
435 // instruction waiting to be verified.
436 if (instList.empty()) {
437 break;
438 } else if (instList.front()->isCompleted()) {
439 unverifiedInst = NULL;
440 unverifiedInst = instList.front();
441 instList.pop_front();
442 } else {
443 break;
444 }
445 }
446 unverifiedInst = NULL;
447}
448
449template <class Impl>
450void
451Checker<Impl>::switchOut()
452{
453 instList.clear();
454}
455
456template <class Impl>
457void
458Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
459{
460}
461
462template <class Impl>
463void
464Checker<Impl>::validateInst(DynInstPtr &inst)
465{
466 if (inst->instAddr() != thread->instAddr()) {
467 warn("%lli: PCs do not match! Inst: %s, checker: %s",
468 curTick(), inst->pcState(), thread->pcState());
469 if (changedPC) {
470 warn("%lli: Changed PCs recently, may not be an error",
471 curTick());
472 } else {
473 handleError(inst);
474 }
475 }
476
477 if (curStaticInst != inst->staticInst) {
478 warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(),
479 curStaticInst->getName(), inst->staticInst->getName());
480 }
481}
482
483template <class Impl>
484void
485Checker<Impl>::validateExecution(DynInstPtr &inst)
486{
487 uint64_t checker_val;
488 uint64_t inst_val;
489 int idx = -1;
490 bool result_mismatch = false;
491
492 if (inst->isUnverifiable()) {
493 // Unverifiable instructions assume they were executed
494 // properly by the CPU. Grab the result from the
495 // instruction and write it to the register.
496 copyResult(inst, 0, idx);
497 } else if (inst->numDestRegs() > 0 && !result.empty()) {
498 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n",
499 inst->numDestRegs(), result.size());
500 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) {
501 result.front().get(checker_val);
502 result.pop();
503 inst_val = 0;
504 inst->template popResult<uint64_t>(inst_val);
505 if (checker_val != inst_val) {
506 result_mismatch = true;
507 idx = i;
508 break;
509 }
510 }
511 } // Checker CPU checks all the saved results in the dyninst passed by
512 // the cpu model being checked against the saved results present in
513 // the static inst executed in the Checker. Sometimes the number
514 // of saved results differs between the dyninst and static inst, but
515 // this is ok and not a bug. May be worthwhile to try and correct this.
516
517 if (result_mismatch) {
518 warn("%lli: Instruction results do not match! (Values may not "
519 "actually be integers) Inst: %#x, checker: %#x",
520 curTick(), inst_val, checker_val);
521
522 // It's useful to verify load values from memory, but in MP
523 // systems the value obtained at execute may be different than
524 // the value obtained at completion. Similarly DMA can
525 // present the same problem on even UP systems. Thus there is
526 // the option to only warn on loads having a result error.
527 // The load/store queue in Detailed CPU can also cause problems
528 // if load/store forwarding is allowed.
529 if (inst->isLoad() && warnOnlyOnLoadError) {
530 copyResult(inst, inst_val, idx);
531 } else {
532 handleError(inst);
533 }
534 }
535
536 if (inst->nextInstAddr() != thread->nextInstAddr()) {
537 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
538 "checker: %#x",
539 curTick(), inst->nextInstAddr(), thread->nextInstAddr());
540 handleError(inst);
541 }
542
543 // Checking side effect registers can be difficult if they are not
544 // checked simultaneously with the execution of the instruction.
545 // This is because other valid instructions may have modified
546 // these registers in the meantime, and their values are not
547 // stored within the DynInst.
548 while (!miscRegIdxs.empty()) {
549 int misc_reg_idx = miscRegIdxs.front();
550 miscRegIdxs.pop();
551
552 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
553 thread->readMiscRegNoEffect(misc_reg_idx)) {
554 warn("%lli: Misc reg idx %i (side effect) does not match! "
555 "Inst: %#x, checker: %#x",
556 curTick(), misc_reg_idx,
557 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
558 thread->readMiscRegNoEffect(misc_reg_idx));
559 handleError(inst);
560 }
561 }
562}
563
564
565// This function is weird, if it is called it means the Checker and
566// O3 have diverged, so panic is called for now. It may be useful
567// to resynch states and continue if the divergence is a false positive
568template <class Impl>
569void
570Checker<Impl>::validateState()
571{
572 if (updateThisCycle) {
573 // Change this back to warn if divergences end up being false positives
574 panic("%lli: Instruction PC %#x results didn't match up, copying all "
575 "registers from main CPU", curTick(), unverifiedInst->instAddr());
576
577 // Terribly convoluted way to make sure O3 model does not implode
578 bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
579 unverifiedInst->thread->noSquashFromTC = true;
580
581 // Heavy-weight copying of all registers
582 thread->copyArchRegs(unverifiedInst->tcBase());
583 unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
584
585 // Set curStaticInst to unverifiedInst->staticInst
586 curStaticInst = unverifiedInst->staticInst;
587 // Also advance the PC. Hopefully no PC-based events happened.
588 advancePC(NoFault);
589 updateThisCycle = false;
590 }
591}
592
593template <class Impl>
594void
595Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
596 int start_idx)
597{
598 // We've already popped one dest off the queue,
599 // so do the fix-up then start with the next dest reg;
600 if (start_idx >= 0) {
601 RegIndex idx = inst->destRegIdx(start_idx);
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