1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <list>
32#include <string>
33
34#include "base/refcnt.hh"
35#include "cpu/base_dyn_inst.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/static_inst.hh"
40#include "mem/packet_impl.hh"
41#include "sim/byteswap.hh"
42#include "sim/sim_object.hh"
43#include "sim/stats.hh"
44
45#if FULL_SYSTEM
46#include "arch/vtophys.hh"
47#endif // FULL_SYSTEM
48
49using namespace std;
50//The CheckerCPU does alpha only
51using namespace AlphaISA;
52
53template <class DynInstPtr>
54void
55Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
56{
57 DynInstPtr inst;
58
59 // Either check this instruction, or add it to a list of
60 // instructions waiting to be checked. Instructions must be
61 // checked in program order, so if a store has committed yet not
62 // completed, there may be some instructions that are waiting
63 // behind it that have completed and must be checked.
64 if (!instList.empty()) {
65 if (youngestSN < completed_inst->seqNum) {
66 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
67 completed_inst->seqNum, completed_inst->readPC());
68 instList.push_back(completed_inst);
69 youngestSN = completed_inst->seqNum;
70 }
71
72 if (!instList.front()->isCompleted()) {
73 return;
74 } else {
75 inst = instList.front();
76 instList.pop_front();
77 }
78 } else {
79 if (!completed_inst->isCompleted()) {
80 if (youngestSN < completed_inst->seqNum) {
81 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
82 completed_inst->seqNum, completed_inst->readPC());
83 instList.push_back(completed_inst);
84 youngestSN = completed_inst->seqNum;
85 }
86 return;
87 } else {
88 if (youngestSN < completed_inst->seqNum) {
89 inst = completed_inst;
90 youngestSN = completed_inst->seqNum;
91 } else {
92 return;
93 }
94 }
95 }
96
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <list>
32#include <string>
33
34#include "base/refcnt.hh"
35#include "cpu/base_dyn_inst.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/static_inst.hh"
40#include "mem/packet_impl.hh"
41#include "sim/byteswap.hh"
42#include "sim/sim_object.hh"
43#include "sim/stats.hh"
44
45#if FULL_SYSTEM
46#include "arch/vtophys.hh"
47#endif // FULL_SYSTEM
48
49using namespace std;
50//The CheckerCPU does alpha only
51using namespace AlphaISA;
52
53template <class DynInstPtr>
54void
55Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
56{
57 DynInstPtr inst;
58
59 // Either check this instruction, or add it to a list of
60 // instructions waiting to be checked. Instructions must be
61 // checked in program order, so if a store has committed yet not
62 // completed, there may be some instructions that are waiting
63 // behind it that have completed and must be checked.
64 if (!instList.empty()) {
65 if (youngestSN < completed_inst->seqNum) {
66 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
67 completed_inst->seqNum, completed_inst->readPC());
68 instList.push_back(completed_inst);
69 youngestSN = completed_inst->seqNum;
70 }
71
72 if (!instList.front()->isCompleted()) {
73 return;
74 } else {
75 inst = instList.front();
76 instList.pop_front();
77 }
78 } else {
79 if (!completed_inst->isCompleted()) {
80 if (youngestSN < completed_inst->seqNum) {
81 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
82 completed_inst->seqNum, completed_inst->readPC());
83 instList.push_back(completed_inst);
84 youngestSN = completed_inst->seqNum;
85 }
86 return;
87 } else {
88 if (youngestSN < completed_inst->seqNum) {
89 inst = completed_inst;
90 youngestSN = completed_inst->seqNum;
91 } else {
92 return;
93 }
94 }
95 }
96
|
| 97 unverifiedInst = inst;
98
|
97 // Try to check all instructions that are completed, ending if we
98 // run out of instructions to check or if an instruction is not
99 // yet completed.
100 while (1) {
101 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
102 inst->seqNum, inst->readPC());
103 unverifiedResult.integer = inst->readIntResult();
104 unverifiedReq = inst->req;
105 unverifiedMemData = inst->memData;
106 numCycles++;
107
108 Fault fault = NoFault;
109
110 // maintain $r0 semantics
111 thread->setIntReg(ZeroReg, 0);
112#ifdef TARGET_ALPHA
113 thread->setFloatRegDouble(ZeroReg, 0.0);
114#endif // TARGET_ALPHA
115
116 // Check if any recent PC changes match up with anything we
117 // expect to happen. This is mostly to check if traps or
118 // PC-based events have occurred in both the checker and CPU.
119 if (changedPC) {
120 DPRINTF(Checker, "Changed PC recently to %#x\n",
121 thread->readPC());
122 if (willChangePC) {
123 if (newPC == thread->readPC()) {
124 DPRINTF(Checker, "Changed PC matches expected PC\n");
125 } else {
126 warn("%lli: Changed PC does not match expected PC, "
127 "changed: %#x, expected: %#x",
128 curTick, thread->readPC(), newPC);
129 CheckerCPU::handleError();
130 }
131 willChangePC = false;
132 }
133 changedPC = false;
134 }
135 if (changedNextPC) {
136 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
137 thread->readNextPC());
138 changedNextPC = false;
139 }
140
141 // Try to fetch the instruction
142
143#if FULL_SYSTEM
144#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
145#else
146#define IFETCH_FLAGS(pc) 0
147#endif
148
149 uint64_t fetch_PC = thread->readPC() & ~3;
150
151 // set up memory request for instruction fetch
152 memReq = new Request(inst->threadNumber, fetch_PC,
153 sizeof(uint32_t),
154 IFETCH_FLAGS(thread->readPC()),
155 fetch_PC, thread->readCpuId(), inst->threadNumber);
156
157 bool succeeded = translateInstReq(memReq);
158
159 if (!succeeded) {
160 if (inst->getFault() == NoFault) {
161 // In this case the instruction was not a dummy
162 // instruction carrying an ITB fault. In the single
163 // threaded case the ITB should still be able to
164 // translate this instruction; in the SMT case it's
165 // possible that its ITB entry was kicked out.
166 warn("%lli: Instruction PC %#x was not found in the ITB!",
167 curTick, thread->readPC());
168 handleError(inst);
169
170 // go to the next instruction
171 thread->setPC(thread->readNextPC());
172 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
173
| 99 // Try to check all instructions that are completed, ending if we
100 // run out of instructions to check or if an instruction is not
101 // yet completed.
102 while (1) {
103 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
104 inst->seqNum, inst->readPC());
105 unverifiedResult.integer = inst->readIntResult();
106 unverifiedReq = inst->req;
107 unverifiedMemData = inst->memData;
108 numCycles++;
109
110 Fault fault = NoFault;
111
112 // maintain $r0 semantics
113 thread->setIntReg(ZeroReg, 0);
114#ifdef TARGET_ALPHA
115 thread->setFloatRegDouble(ZeroReg, 0.0);
116#endif // TARGET_ALPHA
117
118 // Check if any recent PC changes match up with anything we
119 // expect to happen. This is mostly to check if traps or
120 // PC-based events have occurred in both the checker and CPU.
121 if (changedPC) {
122 DPRINTF(Checker, "Changed PC recently to %#x\n",
123 thread->readPC());
124 if (willChangePC) {
125 if (newPC == thread->readPC()) {
126 DPRINTF(Checker, "Changed PC matches expected PC\n");
127 } else {
128 warn("%lli: Changed PC does not match expected PC, "
129 "changed: %#x, expected: %#x",
130 curTick, thread->readPC(), newPC);
131 CheckerCPU::handleError();
132 }
133 willChangePC = false;
134 }
135 changedPC = false;
136 }
137 if (changedNextPC) {
138 DPRINTF(Checker, "Changed NextPC recently to %#x\n",
139 thread->readNextPC());
140 changedNextPC = false;
141 }
142
143 // Try to fetch the instruction
144
145#if FULL_SYSTEM
146#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
147#else
148#define IFETCH_FLAGS(pc) 0
149#endif
150
151 uint64_t fetch_PC = thread->readPC() & ~3;
152
153 // set up memory request for instruction fetch
154 memReq = new Request(inst->threadNumber, fetch_PC,
155 sizeof(uint32_t),
156 IFETCH_FLAGS(thread->readPC()),
157 fetch_PC, thread->readCpuId(), inst->threadNumber);
158
159 bool succeeded = translateInstReq(memReq);
160
161 if (!succeeded) {
162 if (inst->getFault() == NoFault) {
163 // In this case the instruction was not a dummy
164 // instruction carrying an ITB fault. In the single
165 // threaded case the ITB should still be able to
166 // translate this instruction; in the SMT case it's
167 // possible that its ITB entry was kicked out.
168 warn("%lli: Instruction PC %#x was not found in the ITB!",
169 curTick, thread->readPC());
170 handleError(inst);
171
172 // go to the next instruction
173 thread->setPC(thread->readNextPC());
174 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
175
|
174 return;
| 176 break;
|
175 } else {
176 // The instruction is carrying an ITB fault. Handle
177 // the fault and see if our results match the CPU on
178 // the next tick().
179 fault = inst->getFault();
180 }
181 }
182
183 if (fault == NoFault) {
184 Packet *pkt = new Packet(memReq, Packet::ReadReq,
185 Packet::Broadcast);
186
187 pkt->dataStatic(&machInst);
188
189 icachePort->sendFunctional(pkt);
190
191 delete pkt;
192
193 // keep an instruction count
194 numInst++;
195
196 // decode the instruction
197 machInst = gtoh(machInst);
198 // Checks that the instruction matches what we expected it to be.
199 // Checks both the machine instruction and the PC.
200 validateInst(inst);
201
202 curStaticInst = StaticInst::decode(makeExtMI(machInst,
| 177 } else {
178 // The instruction is carrying an ITB fault. Handle
179 // the fault and see if our results match the CPU on
180 // the next tick().
181 fault = inst->getFault();
182 }
183 }
184
185 if (fault == NoFault) {
186 Packet *pkt = new Packet(memReq, Packet::ReadReq,
187 Packet::Broadcast);
188
189 pkt->dataStatic(&machInst);
190
191 icachePort->sendFunctional(pkt);
192
193 delete pkt;
194
195 // keep an instruction count
196 numInst++;
197
198 // decode the instruction
199 machInst = gtoh(machInst);
200 // Checks that the instruction matches what we expected it to be.
201 // Checks both the machine instruction and the PC.
202 validateInst(inst);
203
204 curStaticInst = StaticInst::decode(makeExtMI(machInst,
|
203 thread->getTC()));
| 205 thread->readPC()));
|
204
205#if FULL_SYSTEM
206 thread->setInst(machInst);
207#endif // FULL_SYSTEM
208
209 fault = inst->getFault();
210 }
211
212 // Discard fetch's memReq.
213 delete memReq;
214 memReq = NULL;
215
216 // Either the instruction was a fault and we should process the fault,
217 // or we should just go ahead execute the instruction. This assumes
218 // that the instruction is properly marked as a fault.
219 if (fault == NoFault) {
220
221 thread->funcExeInst++;
222
| 206
207#if FULL_SYSTEM
208 thread->setInst(machInst);
209#endif // FULL_SYSTEM
210
211 fault = inst->getFault();
212 }
213
214 // Discard fetch's memReq.
215 delete memReq;
216 memReq = NULL;
217
218 // Either the instruction was a fault and we should process the fault,
219 // or we should just go ahead execute the instruction. This assumes
220 // that the instruction is properly marked as a fault.
221 if (fault == NoFault) {
222
223 thread->funcExeInst++;
224
|
223 fault = curStaticInst->execute(this, NULL);
| 225 if (!inst->isUnverifiable())
226 fault = curStaticInst->execute(this, NULL);
|
224
225 // Checks to make sure instrution results are correct.
226 validateExecution(inst);
227
228 if (curStaticInst->isLoad()) {
229 ++numLoad;
230 }
231 }
232
233 if (fault != NoFault) {
234#if FULL_SYSTEM
235 fault->invoke(tc);
236 willChangePC = true;
237 newPC = thread->readPC();
238 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
239#endif
240 } else {
241#if THE_ISA != MIPS_ISA
242 // go to the next instruction
243 thread->setPC(thread->readNextPC());
244 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
245#else
246 // go to the next instruction
247 thread->setPC(thread->readNextPC());
248 thread->setNextPC(thread->readNextNPC());
249 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
250#endif
251
252 }
253
254#if FULL_SYSTEM
255 // @todo: Determine if these should happen only if the
256 // instruction hasn't faulted. In the SimpleCPU case this may
257 // not be true, but in the O3 or Ozone case this may be true.
258 Addr oldpc;
259 int count = 0;
260 do {
261 oldpc = thread->readPC();
262 system->pcEventQueue.service(tc);
263 count++;
264 } while (oldpc != thread->readPC());
265 if (count > 1) {
266 willChangePC = true;
267 newPC = thread->readPC();
268 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
269 }
270#endif
271
272 // @todo: Optionally can check all registers. (Or just those
273 // that have been modified).
274 validateState();
275
276 if (memReq) {
277 delete memReq;
278 memReq = NULL;
279 }
280
281 // Continue verifying instructions if there's another completed
282 // instruction waiting to be verified.
283 if (instList.empty()) {
284 break;
285 } else if (instList.front()->isCompleted()) {
286 inst = instList.front();
287 instList.pop_front();
288 } else {
289 break;
290 }
291 }
| 227
228 // Checks to make sure instrution results are correct.
229 validateExecution(inst);
230
231 if (curStaticInst->isLoad()) {
232 ++numLoad;
233 }
234 }
235
236 if (fault != NoFault) {
237#if FULL_SYSTEM
238 fault->invoke(tc);
239 willChangePC = true;
240 newPC = thread->readPC();
241 DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
242#endif
243 } else {
244#if THE_ISA != MIPS_ISA
245 // go to the next instruction
246 thread->setPC(thread->readNextPC());
247 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
248#else
249 // go to the next instruction
250 thread->setPC(thread->readNextPC());
251 thread->setNextPC(thread->readNextNPC());
252 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
253#endif
254
255 }
256
257#if FULL_SYSTEM
258 // @todo: Determine if these should happen only if the
259 // instruction hasn't faulted. In the SimpleCPU case this may
260 // not be true, but in the O3 or Ozone case this may be true.
261 Addr oldpc;
262 int count = 0;
263 do {
264 oldpc = thread->readPC();
265 system->pcEventQueue.service(tc);
266 count++;
267 } while (oldpc != thread->readPC());
268 if (count > 1) {
269 willChangePC = true;
270 newPC = thread->readPC();
271 DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
272 }
273#endif
274
275 // @todo: Optionally can check all registers. (Or just those
276 // that have been modified).
277 validateState();
278
279 if (memReq) {
280 delete memReq;
281 memReq = NULL;
282 }
283
284 // Continue verifying instructions if there's another completed
285 // instruction waiting to be verified.
286 if (instList.empty()) {
287 break;
288 } else if (instList.front()->isCompleted()) {
289 inst = instList.front();
290 instList.pop_front();
291 } else {
292 break;
293 }
294 }
|
| 295 unverifiedInst = NULL;
|
292}
293
294template <class DynInstPtr>
295void
296Checker<DynInstPtr>::switchOut()
297{
298 instList.clear();
299}
300
301template <class DynInstPtr>
302void
303Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
304{
305}
306
307template <class DynInstPtr>
308void
309Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
310{
311 if (inst->readPC() != thread->readPC()) {
312 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
313 curTick, inst->readPC(), thread->readPC());
314 if (changedPC) {
315 warn("%lli: Changed PCs recently, may not be an error",
316 curTick);
317 } else {
318 handleError(inst);
319 }
320 }
321
322 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
323
324 if (mi != machInst) {
325 warn("%lli: Binary instructions do not match! Inst: %#x, "
326 "checker: %#x",
327 curTick, mi, machInst);
328 handleError(inst);
329 }
330}
331
332template <class DynInstPtr>
333void
334Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
335{
336 bool result_mismatch = false;
337 if (inst->numDestRegs()) {
338 // @todo: Support more destination registers.
339 if (inst->isUnverifiable()) {
340 // Unverifiable instructions assume they were executed
341 // properly by the CPU. Grab the result from the
342 // instruction and write it to the register.
343 copyResult(inst);
344 } else if (result.integer != inst->readIntResult()) {
345 result_mismatch = true;
346 }
347 }
348
349 if (result_mismatch) {
350 warn("%lli: Instruction results do not match! (Values may not "
351 "actually be integers) Inst: %#x, checker: %#x",
352 curTick, inst->readIntResult(), result.integer);
353
354 // It's useful to verify load values from memory, but in MP
355 // systems the value obtained at execute may be different than
356 // the value obtained at completion. Similarly DMA can
357 // present the same problem on even UP systems. Thus there is
358 // the option to only warn on loads having a result error.
359 if (inst->isLoad() && warnOnlyOnLoadError) {
360 copyResult(inst);
361 } else {
362 handleError(inst);
363 }
364 }
365
366 if (inst->readNextPC() != thread->readNextPC()) {
367 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
368 "checker: %#x",
369 curTick, inst->readNextPC(), thread->readNextPC());
370 handleError(inst);
371 }
372
373 // Checking side effect registers can be difficult if they are not
374 // checked simultaneously with the execution of the instruction.
375 // This is because other valid instructions may have modified
376 // these registers in the meantime, and their values are not
377 // stored within the DynInst.
378 while (!miscRegIdxs.empty()) {
379 int misc_reg_idx = miscRegIdxs.front();
380 miscRegIdxs.pop();
381
382 if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
383 thread->readMiscReg(misc_reg_idx)) {
384 warn("%lli: Misc reg idx %i (side effect) does not match! "
385 "Inst: %#x, checker: %#x",
386 curTick, misc_reg_idx,
387 inst->tcBase()->readMiscReg(misc_reg_idx),
388 thread->readMiscReg(misc_reg_idx));
389 handleError(inst);
390 }
391 }
392}
393
394template <class DynInstPtr>
395void
396Checker<DynInstPtr>::validateState()
397{
| 296}
297
298template <class DynInstPtr>
299void
300Checker<DynInstPtr>::switchOut()
301{
302 instList.clear();
303}
304
305template <class DynInstPtr>
306void
307Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
308{
309}
310
311template <class DynInstPtr>
312void
313Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
314{
315 if (inst->readPC() != thread->readPC()) {
316 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
317 curTick, inst->readPC(), thread->readPC());
318 if (changedPC) {
319 warn("%lli: Changed PCs recently, may not be an error",
320 curTick);
321 } else {
322 handleError(inst);
323 }
324 }
325
326 MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
327
328 if (mi != machInst) {
329 warn("%lli: Binary instructions do not match! Inst: %#x, "
330 "checker: %#x",
331 curTick, mi, machInst);
332 handleError(inst);
333 }
334}
335
336template <class DynInstPtr>
337void
338Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
339{
340 bool result_mismatch = false;
341 if (inst->numDestRegs()) {
342 // @todo: Support more destination registers.
343 if (inst->isUnverifiable()) {
344 // Unverifiable instructions assume they were executed
345 // properly by the CPU. Grab the result from the
346 // instruction and write it to the register.
347 copyResult(inst);
348 } else if (result.integer != inst->readIntResult()) {
349 result_mismatch = true;
350 }
351 }
352
353 if (result_mismatch) {
354 warn("%lli: Instruction results do not match! (Values may not "
355 "actually be integers) Inst: %#x, checker: %#x",
356 curTick, inst->readIntResult(), result.integer);
357
358 // It's useful to verify load values from memory, but in MP
359 // systems the value obtained at execute may be different than
360 // the value obtained at completion. Similarly DMA can
361 // present the same problem on even UP systems. Thus there is
362 // the option to only warn on loads having a result error.
363 if (inst->isLoad() && warnOnlyOnLoadError) {
364 copyResult(inst);
365 } else {
366 handleError(inst);
367 }
368 }
369
370 if (inst->readNextPC() != thread->readNextPC()) {
371 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
372 "checker: %#x",
373 curTick, inst->readNextPC(), thread->readNextPC());
374 handleError(inst);
375 }
376
377 // Checking side effect registers can be difficult if they are not
378 // checked simultaneously with the execution of the instruction.
379 // This is because other valid instructions may have modified
380 // these registers in the meantime, and their values are not
381 // stored within the DynInst.
382 while (!miscRegIdxs.empty()) {
383 int misc_reg_idx = miscRegIdxs.front();
384 miscRegIdxs.pop();
385
386 if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
387 thread->readMiscReg(misc_reg_idx)) {
388 warn("%lli: Misc reg idx %i (side effect) does not match! "
389 "Inst: %#x, checker: %#x",
390 curTick, misc_reg_idx,
391 inst->tcBase()->readMiscReg(misc_reg_idx),
392 thread->readMiscReg(misc_reg_idx));
393 handleError(inst);
394 }
395 }
396}
397
398template <class DynInstPtr>
399void
400Checker<DynInstPtr>::validateState()
401{
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| 402 if (updateThisCycle) {
403 warn("%lli: Instruction PC %#x results didn't match up, copying all "
404 "registers from main CPU", curTick, unverifiedInst->readPC());
405 // Heavy-weight copying of all registers
406 cpuXC->copyArchRegs(unverifiedInst->xcBase());
407 // Also advance the PC. Hopefully no PC-based events happened.
408#if THE_ISA != MIPS_ISA
409 // go to the next instruction
410 cpuXC->setPC(cpuXC->readNextPC());
411 cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
412#else
413 // go to the next instruction
414 cpuXC->setPC(cpuXC->readNextPC());
415 cpuXC->setNextPC(cpuXC->readNextNPC());
416 cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
417#endif
418 updateThisCycle = false;
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398}
399
400template <class DynInstPtr>
401void
402Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
403{
404 RegIndex idx = inst->destRegIdx(0);
405 if (idx < TheISA::FP_Base_DepTag) {
406 thread->setIntReg(idx, inst->readIntResult());
407 } else if (idx < TheISA::Fpcr_DepTag) {
408 thread->setFloatRegBits(idx, inst->readIntResult());
409 } else {
410 thread->setMiscReg(idx, inst->readIntResult());
411 }
412}
413
414template <class DynInstPtr>
415void
416Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
417{
418 cprintf("Error detected, instruction information:\n");
419 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
420 "Completed:%i\n",
421 inst->readPC(),
422 inst->readNextPC(),
423 inst->seqNum,
424 inst->threadNumber,
425 inst->isCompleted());
426 inst->dump();
427 CheckerCPU::dumpAndExit();
428}
429
430template <class DynInstPtr>
431void
432Checker<DynInstPtr>::dumpInsts()
433{
434 int num = 0;
435
436 InstListIt inst_list_it = --(instList.end());
437
438 cprintf("Inst list size: %i\n", instList.size());
439
440 while (inst_list_it != instList.end())
441 {
442 cprintf("Instruction:%i\n",
443 num);
444
445 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
446 "Completed:%i\n",
447 (*inst_list_it)->readPC(),
448 (*inst_list_it)->seqNum,
449 (*inst_list_it)->threadNumber,
450 (*inst_list_it)->isCompleted());
451
452 cprintf("\n");
453
454 inst_list_it--;
455 ++num;
456 }
457
458}
| 419}
420
421template <class DynInstPtr>
422void
423Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
424{
425 RegIndex idx = inst->destRegIdx(0);
426 if (idx < TheISA::FP_Base_DepTag) {
427 thread->setIntReg(idx, inst->readIntResult());
428 } else if (idx < TheISA::Fpcr_DepTag) {
429 thread->setFloatRegBits(idx, inst->readIntResult());
430 } else {
431 thread->setMiscReg(idx, inst->readIntResult());
432 }
433}
434
435template <class DynInstPtr>
436void
437Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
438{
439 cprintf("Error detected, instruction information:\n");
440 cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
441 "Completed:%i\n",
442 inst->readPC(),
443 inst->readNextPC(),
444 inst->seqNum,
445 inst->threadNumber,
446 inst->isCompleted());
447 inst->dump();
448 CheckerCPU::dumpAndExit();
449}
450
451template <class DynInstPtr>
452void
453Checker<DynInstPtr>::dumpInsts()
454{
455 int num = 0;
456
457 InstListIt inst_list_it = --(instList.end());
458
459 cprintf("Inst list size: %i\n", instList.size());
460
461 while (inst_list_it != instList.end())
462 {
463 cprintf("Instruction:%i\n",
464 num);
465
466 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
467 "Completed:%i\n",
468 (*inst_list_it)->readPC(),
469 (*inst_list_it)->seqNum,
470 (*inst_list_it)->threadNumber,
471 (*inst_list_it)->isCompleted());
472
473 cprintf("\n");
474
475 inst_list_it--;
476 ++num;
477 }
478
479}
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