1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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398template <class DynInstPtr>
399void
400Checker<DynInstPtr>::validateState()
401{
402 if (updateThisCycle) {
403 warn("%lli: Instruction PC %#x results didn't match up, copying all "
404 "registers from main CPU", curTick, unverifiedInst->readPC());
405 // Heavy-weight copying of all registers
406 cpuXC->copyArchRegs(unverifiedInst->xcBase());
407 // Also advance the PC. Hopefully no PC-based events happened.
408#if THE_ISA != MIPS_ISA
409 // go to the next instruction
410 cpuXC->setPC(cpuXC->readNextPC());
411 cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
412#else
413 // go to the next instruction
414 cpuXC->setPC(cpuXC->readNextPC());
415 cpuXC->setNextPC(cpuXC->readNextNPC());
416 cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
417#endif
418 updateThisCycle = false;
419}
420
421template <class DynInstPtr>
422void
423Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
424{
425 RegIndex idx = inst->destRegIdx(0);
426 if (idx < TheISA::FP_Base_DepTag) {

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