cpu.cc (8887:20ea02da9c53) cpu.cc (8949:3fa1ee293096)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 156 unchanged lines hidden (view full) ---

165 pAddr = memReq->getPaddr();
166 checked_flags = true;
167 }
168
169 // Now do the access
170 if (fault == NoFault &&
171 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
172 PacketPtr pkt = new Packet(memReq,
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 156 unchanged lines hidden (view full) ---

165 pAddr = memReq->getPaddr();
166 checked_flags = true;
167 }
168
169 // Now do the access
170 if (fault == NoFault &&
171 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
172 PacketPtr pkt = new Packet(memReq,
173 memReq->isLLSC() ?
174 MemCmd::LoadLockedReq : MemCmd::ReadReq,
175 Packet::Broadcast);
173 memReq->isLLSC() ?
174 MemCmd::LoadLockedReq :
175 MemCmd::ReadReq);
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access

--- 169 unchanged lines hidden --- 		176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access

--- 169 unchanged lines hidden ---