cpu.cc (8876:44f8e7bb7fdf) cpu.cc (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/full_system.hh"
55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{

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79 changedPC = willChangePC = changedNextPC = false;
80
81 exitOnError = p->exitOnError;
82 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
83 itb = p->itb;
84 dtb = p->dtb;
85 systemPtr = NULL;
86 workload = p->workload;
56#include "sim/tlb.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{

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80 changedPC = willChangePC = changedNextPC = false;
81
82 exitOnError = p->exitOnError;
83 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
84 itb = p->itb;
85 dtb = p->dtb;
86 systemPtr = NULL;
87 workload = p->workload;
87 // XXX: This is a hack to get this to work some
88 thread = new SimpleThread(this, /* thread_num */ 0,
89 workload.size() ? workload[0] : NULL, itb, dtb);
88 thread = NULL;
90
89
91 tc = thread->getTC();
92 threadContexts.push_back(tc);
93
94 updateOnError = true;
95}
96
97CheckerCPU::~CheckerCPU()
98{
99}
100
101void
102CheckerCPU::setSystem(System *system)
103{
104 systemPtr = system;
105
90 updateOnError = true;
91}
92
93CheckerCPU::~CheckerCPU()
94{
95}
96
97void
98CheckerCPU::setSystem(System *system)
99{
100 systemPtr = system;
101
106 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
102 if (FullSystem) {
103 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
104 } else {
105 thread = new SimpleThread(this, 0, systemPtr,
106 workload.size() ? workload[0] : NULL,
107 itb, dtb);
108 }
107
108 tc = thread->getTC();
109 threadContexts.push_back(tc);
109
110 tc = thread->getTC();
111 threadContexts.push_back(tc);
110 delete thread->kernelStats;
111 thread->kernelStats = NULL;
112 thread->kernelStats = NULL;
113 // Thread should never be null after this
114 assert(thread != NULL);
112}
113
114void
115}
116
117void
115CheckerCPU::setIcachePort(Port *icache_port)
118CheckerCPU::setIcachePort(CpuPort *icache_port)
116{
117 icachePort = icache_port;
118}
119
120void
119{
120 icachePort = icache_port;
121}
122
123void
121CheckerCPU::setDcachePort(Port *dcache_port)
124CheckerCPU::setDcachePort(CpuPort *dcache_port)
122{
123 dcachePort = dcache_port;
124}
125
126void
127CheckerCPU::serialize(ostream &os)
128{
129}

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146
147
148 if (secondAddr > addr)
149 size = secondAddr - addr;
150
151 // Need to account for multiple accesses like the Atomic and TimingSimple
152 while (1) {
153 memReq = new Request();
125{
126 dcachePort = dcache_port;
127}
128
129void
130CheckerCPU::serialize(ostream &os)
131{
132}

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149
150
151 if (secondAddr > addr)
152 size = secondAddr - addr;
153
154 // Need to account for multiple accesses like the Atomic and TimingSimple
155 while (1) {
156 memReq = new Request();
154 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
157 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
155
156 // translate to physical address
157 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
158
159 if (!checked_flags && fault == NoFault && unverifiedReq) {
160 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
161 memReq->getPaddr(), memReq->getFlags());
162 pAddr = memReq->getPaddr();

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159 // translate to physical address
160 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
161
162 if (!checked_flags && fault == NoFault && unverifiedReq) {
163 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
164 memReq->getPaddr(), memReq->getFlags());
165 pAddr = memReq->getPaddr();

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