cpu.cc (8818:8f354c5a1634) cpu.cc (8832:247fee427324)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 46 unchanged lines hidden (view full) ---

55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 46 unchanged lines hidden (view full) ---

55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{
63 masterId = systemPtr->getMasterId(name());
63}
64
65CheckerCPU::CheckerCPU(Params *p)
66 : BaseCPU(p), thread(NULL), tc(NULL)
67{
68 memReq = NULL;
69 curStaticInst = NULL;
70 curMacroStaticInst = NULL;

--- 165 unchanged lines hidden (view full) ---

236 Addr secondAddr = roundDown(addr + size - 1, blockSize);
237
238 if (secondAddr > addr)
239 size = secondAddr - addr;
240
241 // Need to account for a multiple access like Atomic and Timing CPUs
242 while (1) {
243 memReq = new Request();
64}
65
66CheckerCPU::CheckerCPU(Params *p)
67 : BaseCPU(p), thread(NULL), tc(NULL)
68{
69 memReq = NULL;
70 curStaticInst = NULL;
71 curMacroStaticInst = NULL;

--- 165 unchanged lines hidden (view full) ---

237 Addr secondAddr = roundDown(addr + size - 1, blockSize);
238
239 if (secondAddr > addr)
240 size = secondAddr - addr;
241
242 // Need to account for a multiple access like Atomic and Timing CPUs
243 while (1) {
244 memReq = new Request();
244 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
245 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
245
246 // translate to physical address
247 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
248
249 if (!checked_flags && fault == NoFault && unverifiedReq) {
250 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
251 memReq->getPaddr(), memReq->getFlags());
252 pAddr = memReq->getPaddr();

--- 96 unchanged lines hidden --- 		246
247 // translate to physical address
248 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
249
250 if (!checked_flags && fault == NoFault && unverifiedReq) {
251 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
252 memReq->getPaddr(), memReq->getFlags());
253 pAddr = memReq->getPaddr();

--- 96 unchanged lines hidden ---