cpu.cc (5890:bdef71accd68) | cpu.cc (5891:73084c6bb183) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 145 unchanged lines hidden (view full) --- 154CheckerCPU::read(Addr addr, T &data, unsigned flags) 155{ 156 // need to fill in CPU & thread IDs here 157 memReq = new Request(); 158 159 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 160 161 // translate to physical address | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 145 unchanged lines hidden (view full) --- 154CheckerCPU::read(Addr addr, T &data, unsigned flags) 155{ 156 // need to fill in CPU & thread IDs here 157 memReq = new Request(); 158 159 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 160 161 // translate to physical address |
162 dtb->translate(memReq, tc, false); | 162 dtb->translateAtomic(memReq, tc, false); |
163 164 PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 165 166 pkt->dataStatic(&data); 167 168 if (!(memReq->isUncacheable())) { 169 // Access memory to see if we have the same data 170 dcachePort->sendFunctional(pkt); --- 53 unchanged lines hidden (view full) --- 224CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 225{ 226 // need to fill in CPU & thread IDs here 227 memReq = new Request(); 228 229 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 230 231 // translate to physical address | 163 164 PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 165 166 pkt->dataStatic(&data); 167 168 if (!(memReq->isUncacheable())) { 169 // Access memory to see if we have the same data 170 dcachePort->sendFunctional(pkt); --- 53 unchanged lines hidden (view full) --- 224CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 225{ 226 // need to fill in CPU & thread IDs here 227 memReq = new Request(); 228 229 memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 230 231 // translate to physical address |
232 dtb->translate(memReq, tc, true); | 232 dtb->translateAtomic(memReq, tc, true); |
233 234 // Can compare the write data and result only if it's cacheable, 235 // not a store conditional, or is a store conditional that 236 // succeeded. 237 // @todo: Verify that actual memory matches up with these values. 238 // Right now it only verifies that the instruction data is the 239 // same as what was in the request that got sent to memory; there 240 // is no verification that it is the same as what is in memory. --- 107 unchanged lines hidden --- | 233 234 // Can compare the write data and result only if it's cacheable, 235 // not a store conditional, or is a store conditional that 236 // succeeded. 237 // @todo: Verify that actual memory matches up with these values. 238 // Right now it only verifies that the instruction data is the 239 // same as what was in the request that got sent to memory; there 240 // is no verification that it is the same as what is in memory. --- 107 unchanged lines hidden --- |