cpu.cc (12748:ae5ce8e42de7) cpu.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2011,2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 55 unchanged lines hidden (view full) ---

64{
65 masterId = systemPtr->getMasterId(this);
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
1/*
2 * Copyright (c) 2011,2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 55 unchanged lines hidden (view full) ---

64{
65 masterId = systemPtr->getMasterId(this);
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
72 memReq = NULL;
73 curStaticInst = NULL;
74 curMacroStaticInst = NULL;
75
76 numInst = 0;
77 startNumInst = 0;
78 numLoad = 0;
79 startNumLoad = 0;
80 youngestSN = 0;

--- 70 unchanged lines hidden (view full) ---

151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;

--- 70 unchanged lines hidden (view full) ---

150 Addr pAddr = 0x0;
151
152
153 if (secondAddr > addr)
154 size = secondAddr - addr;
155
156 // Need to account for multiple accesses like the Atomic and TimingSimple
157 while (1) {
159 memReq = new Request(0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
158 auto mem_req = std::make_shared<Request>(
159 0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
161
162 // translate to physical address
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
163 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
166 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
167 mem_req->getPaddr(), mem_req->getFlags());
168 pAddr = mem_req->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(memReq);
174 !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(mem_req);
176
177 pkt->dataStatic(data);
178
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
179 if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
187 delete memReq;
188 memReq = NULL;
189 delete pkt;
190 }
191
192 if (fault != NoFault) {
187 delete pkt;
188 }
189
190 if (fault != NoFault) {
193 if (memReq->isPrefetch()) {
191 if (mem_req->isPrefetch()) {
194 fault = NoFault;
195 }
192 fault = NoFault;
193 }
196 delete memReq;
197 memReq = NULL;
198 break;
199 }
200
194 break;
195 }
196
201 if (memReq != NULL) {
202 delete memReq;
203 }
204
205 //If we don't need to access a second cache line, stop now.
206 if (secondAddr <= addr)
207 {
208 break;
209 }
210
211 // Setup for accessing next cache line
212 data += size;

--- 26 unchanged lines hidden (view full) ---

239
240 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
241
242 if (secondAddr > addr)
243 size = secondAddr - addr;
244
245 // Need to account for a multiple access like Atomic and Timing CPUs
246 while (1) {
197 //If we don't need to access a second cache line, stop now.
198 if (secondAddr <= addr)
199 {
200 break;
201 }
202
203 // Setup for accessing next cache line
204 data += size;

--- 26 unchanged lines hidden (view full) ---

231
232 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
233
234 if (secondAddr > addr)
235 size = secondAddr - addr;
236
237 // Need to account for a multiple access like Atomic and Timing CPUs
238 while (1) {
247 memReq = new Request(0, addr, size, flags, masterId,
248 thread->pcState().instAddr(), tc->contextId());
239 auto mem_req = std::make_shared<Request>(
240 0, addr, size, flags, masterId,
241 thread->pcState().instAddr(), tc->contextId());
249
250 // translate to physical address
242
243 // translate to physical address
251 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
244 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
252
253 if (!checked_flags && fault == NoFault && unverifiedReq) {
245
246 if (!checked_flags && fault == NoFault && unverifiedReq) {
254 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
255 memReq->getPaddr(), memReq->getFlags());
256 pAddr = memReq->getPaddr();
247 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
248 mem_req->getPaddr(), mem_req->getFlags());
249 pAddr = mem_req->getPaddr();
257 checked_flags = true;
258 }
259
260 /*
261 * We don't actually check memory for the store because there
262 * is no guarantee it has left the lsq yet, and therefore we
263 * can't verify the memory on stores without lsq snooping
264 * enabled. This is left as future work for the Checker: LSQ snooping
265 * and memory validation after stores have committed.
266 */
250 checked_flags = true;
251 }
252
253 /*
254 * We don't actually check memory for the store because there
255 * is no guarantee it has left the lsq yet, and therefore we
256 * can't verify the memory on stores without lsq snooping
257 * enabled. This is left as future work for the Checker: LSQ snooping
258 * and memory validation after stores have committed.
259 */
267 bool was_prefetch = memReq->isPrefetch();
260 bool was_prefetch = mem_req->isPrefetch();
268
261
269 delete memReq;
270
271 //If we don't need to access a second cache line, stop now.
272 if (fault != NoFault || secondAddr <= addr)
273 {
274 if (fault != NoFault && was_prefetch) {
275 fault = NoFault;
276 }
277 break;
278 }

--- 53 unchanged lines hidden (view full) ---

332{
333 return vtophys(tc, addr);
334}
335
336/**
337 * Checks if the flags set by the Checker and Checkee match.
338 */
339bool
262 //If we don't need to access a second cache line, stop now.
263 if (fault != NoFault || secondAddr <= addr)
264 {
265 if (fault != NoFault && was_prefetch) {
266 fault = NoFault;
267 }
268 break;
269 }

--- 53 unchanged lines hidden (view full) ---

323{
324 return vtophys(tc, addr);
325}
326
327/**
328 * Checks if the flags set by the Checker and Checkee match.
329 */
330bool
340CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
331CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
341 Addr pAddr, int flags)
342{
343 Addr unverifiedVAddr = unverified_req->getVaddr();
344 Addr unverifiedPAddr = unverified_req->getPaddr();
345 int unverifiedFlags = unverified_req->getFlags();
346
347 if (unverifiedVAddr != vAddr ||
348 unverifiedPAddr != pAddr ||

--- 14 unchanged lines hidden --- 		332 Addr pAddr, int flags)
333{
334 Addr unverifiedVAddr = unverified_req->getVaddr();
335 Addr unverifiedPAddr = unverified_req->getPaddr();
336 int unverifiedFlags = unverified_req->getFlags();
337
338 if (unverifiedVAddr != vAddr ||
339 unverifiedPAddr != pAddr ||

--- 14 unchanged lines hidden ---