cpu.cc (10505:38c7a9ea7729) cpu.cc (10653:e3fc6bc7f97e)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 140 unchanged lines hidden (view full) ---

149 Addr pAddr = 0x0;
150
151
152 if (secondAddr > addr)
153 size = secondAddr - addr;
154
155 // Need to account for multiple accesses like the Atomic and TimingSimple
156 while (1) {
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 140 unchanged lines hidden (view full) ---

149 Addr pAddr = 0x0;
150
151
152 if (secondAddr > addr)
153 size = secondAddr - addr;
154
155 // Need to account for multiple accesses like the Atomic and TimingSimple
156 while (1) {
157 memReq = new Request();
158 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
157 memReq = new Request(0, addr, size, flags, masterId,
158 thread->pcState().instAddr(), tc->contextId(), 0);
159
160 // translate to physical address
161 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
162
163 if (!checked_flags && fault == NoFault && unverifiedReq) {
164 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
165 memReq->getPaddr(), memReq->getFlags());
166 pAddr = memReq->getPaddr();

--- 70 unchanged lines hidden (view full) ---

237
238 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
239
240 if (secondAddr > addr)
241 size = secondAddr - addr;
242
243 // Need to account for a multiple access like Atomic and Timing CPUs
244 while (1) {
159
160 // translate to physical address
161 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
162
163 if (!checked_flags && fault == NoFault && unverifiedReq) {
164 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
165 memReq->getPaddr(), memReq->getFlags());
166 pAddr = memReq->getPaddr();

--- 70 unchanged lines hidden (view full) ---

237
238 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
239
240 if (secondAddr > addr)
241 size = secondAddr - addr;
242
243 // Need to account for a multiple access like Atomic and Timing CPUs
244 while (1) {
245 memReq = new Request();
246 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
245 memReq = new Request(0, addr, size, flags, masterId,
246 thread->pcState().instAddr(), tc->contextId(), 0);
247
248 // translate to physical address
249 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
250
251 if (!checked_flags && fault == NoFault && unverifiedReq) {
252 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
253 memReq->getPaddr(), memReq->getFlags());
254 pAddr = memReq->getPaddr();

--- 106 unchanged lines hidden --- 		247
248 // translate to physical address
249 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
250
251 if (!checked_flags && fault == NoFault && unverifiedReq) {
252 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
253 memReq->getPaddr(), memReq->getFlags());
254 pAddr = memReq->getPaddr();

--- 106 unchanged lines hidden ---