1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/full_system.hh"
56#include "sim/tlb.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{
64 masterId = systemPtr->getMasterId(name());
65}
66
67CheckerCPU::CheckerCPU(Params *p)
68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69 tc(NULL), thread(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = changedNextPC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87 workload = p->workload;
88
89 updateOnError = true;
90}
91
92CheckerCPU::~CheckerCPU()
93{
94}
95
96void
97CheckerCPU::setSystem(System *system)
98{
99 const Params *p(dynamic_cast<const Params *>(_params));
100
101 systemPtr = system;
102
103 if (FullSystem) {
104 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
105 p->isa[0], false);
106 } else {
107 thread = new SimpleThread(this, 0, systemPtr,
108 workload.size() ? workload[0] : NULL,
109 itb, dtb, p->isa[0]);
110 }
111
112 tc = thread->getTC();
113 threadContexts.push_back(tc);
114 thread->kernelStats = NULL;
115 // Thread should never be null after this
116 assert(thread != NULL);
117}
118
119void
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/full_system.hh"
56#include "sim/tlb.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{
64 masterId = systemPtr->getMasterId(name());
65}
66
67CheckerCPU::CheckerCPU(Params *p)
68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69 tc(NULL), thread(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = changedNextPC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87 workload = p->workload;
88
89 updateOnError = true;
90}
91
92CheckerCPU::~CheckerCPU()
93{
94}
95
96void
97CheckerCPU::setSystem(System *system)
98{
99 const Params *p(dynamic_cast<const Params *>(_params));
100
101 systemPtr = system;
102
103 if (FullSystem) {
104 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
105 p->isa[0], false);
106 } else {
107 thread = new SimpleThread(this, 0, systemPtr,
108 workload.size() ? workload[0] : NULL,
109 itb, dtb, p->isa[0]);
110 }
111
112 tc = thread->getTC();
113 threadContexts.push_back(tc);
114 thread->kernelStats = NULL;
115 // Thread should never be null after this
116 assert(thread != NULL);
117}
118
119void
|
127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os)
133{
134}
135
136void
137CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
143{
144 Fault fault = NoFault;
145 unsigned blockSize = dcachePort->peerBlockSize();
146 int fullSize = size;
147 Addr secondAddr = roundDown(addr + size - 1, blockSize);
148 bool checked_flags = false;
149 bool flags_match = true;
150 Addr pAddr = 0x0;
151
152
153 if (secondAddr > addr)
154 size = secondAddr - addr;
155
156 // Need to account for multiple accesses like the Atomic and TimingSimple
157 while (1) {
158 memReq = new Request();
159 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
160
161 // translate to physical address
162 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
163
164 if (!checked_flags && fault == NoFault && unverifiedReq) {
165 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
166 memReq->getPaddr(), memReq->getFlags());
167 pAddr = memReq->getPaddr();
168 checked_flags = true;
169 }
170
171 // Now do the access
172 if (fault == NoFault &&
173 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
174 PacketPtr pkt = new Packet(memReq,
175 memReq->isLLSC() ?
176 MemCmd::LoadLockedReq :
177 MemCmd::ReadReq);
178
179 pkt->dataStatic(data);
180
181 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
182 // Access memory to see if we have the same data
183 dcachePort->sendFunctional(pkt);
184 } else {
185 // Assume the data is correct if it's an uncached access
186 memcpy(data, unverifiedMemData, size);
187 }
188
189 delete memReq;
190 memReq = NULL;
191 delete pkt;
192 }
193
194 if (fault != NoFault) {
195 if (memReq->isPrefetch()) {
196 fault = NoFault;
197 }
198 delete memReq;
199 memReq = NULL;
200 break;
201 }
202
203 if (memReq != NULL) {
204 delete memReq;
205 }
206
207 //If we don't need to access a second cache line, stop now.
208 if (secondAddr <= addr)
209 {
210 break;
211 }
212
213 // Setup for accessing next cache line
214 data += size;
215 unverifiedMemData += size;
216 size = addr + fullSize - secondAddr;
217 addr = secondAddr;
218 }
219
220 if (!flags_match) {
221 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
222 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
223 unverifiedReq->getFlags(), addr, pAddr, flags);
224 handleError();
225 }
226
227 return fault;
228}
229
230Fault
231CheckerCPU::writeMem(uint8_t *data, unsigned size,
232 Addr addr, unsigned flags, uint64_t *res)
233{
234 Fault fault = NoFault;
235 bool checked_flags = false;
236 bool flags_match = true;
237 Addr pAddr = 0x0;
238
239 unsigned blockSize = dcachePort->peerBlockSize();
240 int fullSize = size;
241
242 Addr secondAddr = roundDown(addr + size - 1, blockSize);
243
244 if (secondAddr > addr)
245 size = secondAddr - addr;
246
247 // Need to account for a multiple access like Atomic and Timing CPUs
248 while (1) {
249 memReq = new Request();
250 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
251
252 // translate to physical address
253 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
254
255 if (!checked_flags && fault == NoFault && unverifiedReq) {
256 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
257 memReq->getPaddr(), memReq->getFlags());
258 pAddr = memReq->getPaddr();
259 checked_flags = true;
260 }
261
262 /*
263 * We don't actually check memory for the store because there
264 * is no guarantee it has left the lsq yet, and therefore we
265 * can't verify the memory on stores without lsq snooping
266 * enabled. This is left as future work for the Checker: LSQ snooping
267 * and memory validation after stores have committed.
268 */
269 bool was_prefetch = memReq->isPrefetch();
270
271 delete memReq;
272
273 //If we don't need to access a second cache line, stop now.
274 if (fault != NoFault || secondAddr <= addr)
275 {
276 if (fault != NoFault && was_prefetch) {
277 fault = NoFault;
278 }
279 break;
280 }
281
282 //Update size and access address
283 size = addr + fullSize - secondAddr;
284 //And access the right address.
285 addr = secondAddr;
286 }
287
288 if (!flags_match) {
289 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
290 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
291 unverifiedReq->getFlags(), addr, pAddr, flags);
292 handleError();
293 }
294
295 // Assume the result was the same as the one passed in. This checker
296 // doesn't check if the SC should succeed or fail, it just checks the
297 // value.
298 if (unverifiedReq && res && unverifiedReq->extraDataValid())
299 *res = unverifiedReq->getExtraData();
300
301 // Entire purpose here is to make sure we are getting the
302 // same data to send to the mem system as the CPU did.
303 // Cannot check this is actually what went to memory because
304 // there stores can be in ld/st queue or coherent operations
305 // overwriting values.
306 bool extraData;
307 if (unverifiedReq) {
308 extraData = unverifiedReq->extraDataValid() ?
309 unverifiedReq->getExtraData() : 1;
310 }
311
312 if (unverifiedReq && unverifiedMemData &&
313 memcmp(data, unverifiedMemData, fullSize) && extraData) {
314 warn("%lli: Store value does not match value sent to memory!\
315 data: %#x inst_data: %#x", curTick(), data,
316 unverifiedMemData);
317 handleError();
318 }
319
320 return fault;
321}
322
323Addr
324CheckerCPU::dbg_vtophys(Addr addr)
325{
326 return vtophys(tc, addr);
327}
328
329/**
330 * Checks if the flags set by the Checker and Checkee match.
331 */
332bool
333CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
334 Addr pAddr, int flags)
335{
336 Addr unverifiedVAddr = unverified_req->getVaddr();
337 Addr unverifiedPAddr = unverified_req->getPaddr();
338 int unverifiedFlags = unverified_req->getFlags();
339
340 if (unverifiedVAddr != vAddr ||
341 unverifiedPAddr != pAddr ||
342 unverifiedFlags != flags) {
343 return false;
344 }
345
346 return true;
347}
348
349void
350CheckerCPU::dumpAndExit()
351{
352 warn("%lli: Checker PC:%s",
353 curTick(), thread->pcState());
354 panic("Checker found an error!");
355}
| 127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os)
133{
134}
135
136void
137CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
143{
144 Fault fault = NoFault;
145 unsigned blockSize = dcachePort->peerBlockSize();
146 int fullSize = size;
147 Addr secondAddr = roundDown(addr + size - 1, blockSize);
148 bool checked_flags = false;
149 bool flags_match = true;
150 Addr pAddr = 0x0;
151
152
153 if (secondAddr > addr)
154 size = secondAddr - addr;
155
156 // Need to account for multiple accesses like the Atomic and TimingSimple
157 while (1) {
158 memReq = new Request();
159 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
160
161 // translate to physical address
162 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
163
164 if (!checked_flags && fault == NoFault && unverifiedReq) {
165 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
166 memReq->getPaddr(), memReq->getFlags());
167 pAddr = memReq->getPaddr();
168 checked_flags = true;
169 }
170
171 // Now do the access
172 if (fault == NoFault &&
173 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
174 PacketPtr pkt = new Packet(memReq,
175 memReq->isLLSC() ?
176 MemCmd::LoadLockedReq :
177 MemCmd::ReadReq);
178
179 pkt->dataStatic(data);
180
181 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
182 // Access memory to see if we have the same data
183 dcachePort->sendFunctional(pkt);
184 } else {
185 // Assume the data is correct if it's an uncached access
186 memcpy(data, unverifiedMemData, size);
187 }
188
189 delete memReq;
190 memReq = NULL;
191 delete pkt;
192 }
193
194 if (fault != NoFault) {
195 if (memReq->isPrefetch()) {
196 fault = NoFault;
197 }
198 delete memReq;
199 memReq = NULL;
200 break;
201 }
202
203 if (memReq != NULL) {
204 delete memReq;
205 }
206
207 //If we don't need to access a second cache line, stop now.
208 if (secondAddr <= addr)
209 {
210 break;
211 }
212
213 // Setup for accessing next cache line
214 data += size;
215 unverifiedMemData += size;
216 size = addr + fullSize - secondAddr;
217 addr = secondAddr;
218 }
219
220 if (!flags_match) {
221 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
222 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
223 unverifiedReq->getFlags(), addr, pAddr, flags);
224 handleError();
225 }
226
227 return fault;
228}
229
230Fault
231CheckerCPU::writeMem(uint8_t *data, unsigned size,
232 Addr addr, unsigned flags, uint64_t *res)
233{
234 Fault fault = NoFault;
235 bool checked_flags = false;
236 bool flags_match = true;
237 Addr pAddr = 0x0;
238
239 unsigned blockSize = dcachePort->peerBlockSize();
240 int fullSize = size;
241
242 Addr secondAddr = roundDown(addr + size - 1, blockSize);
243
244 if (secondAddr > addr)
245 size = secondAddr - addr;
246
247 // Need to account for a multiple access like Atomic and Timing CPUs
248 while (1) {
249 memReq = new Request();
250 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
251
252 // translate to physical address
253 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
254
255 if (!checked_flags && fault == NoFault && unverifiedReq) {
256 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
257 memReq->getPaddr(), memReq->getFlags());
258 pAddr = memReq->getPaddr();
259 checked_flags = true;
260 }
261
262 /*
263 * We don't actually check memory for the store because there
264 * is no guarantee it has left the lsq yet, and therefore we
265 * can't verify the memory on stores without lsq snooping
266 * enabled. This is left as future work for the Checker: LSQ snooping
267 * and memory validation after stores have committed.
268 */
269 bool was_prefetch = memReq->isPrefetch();
270
271 delete memReq;
272
273 //If we don't need to access a second cache line, stop now.
274 if (fault != NoFault || secondAddr <= addr)
275 {
276 if (fault != NoFault && was_prefetch) {
277 fault = NoFault;
278 }
279 break;
280 }
281
282 //Update size and access address
283 size = addr + fullSize - secondAddr;
284 //And access the right address.
285 addr = secondAddr;
286 }
287
288 if (!flags_match) {
289 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
290 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
291 unverifiedReq->getFlags(), addr, pAddr, flags);
292 handleError();
293 }
294
295 // Assume the result was the same as the one passed in. This checker
296 // doesn't check if the SC should succeed or fail, it just checks the
297 // value.
298 if (unverifiedReq && res && unverifiedReq->extraDataValid())
299 *res = unverifiedReq->getExtraData();
300
301 // Entire purpose here is to make sure we are getting the
302 // same data to send to the mem system as the CPU did.
303 // Cannot check this is actually what went to memory because
304 // there stores can be in ld/st queue or coherent operations
305 // overwriting values.
306 bool extraData;
307 if (unverifiedReq) {
308 extraData = unverifiedReq->extraDataValid() ?
309 unverifiedReq->getExtraData() : 1;
310 }
311
312 if (unverifiedReq && unverifiedMemData &&
313 memcmp(data, unverifiedMemData, fullSize) && extraData) {
314 warn("%lli: Store value does not match value sent to memory!\
315 data: %#x inst_data: %#x", curTick(), data,
316 unverifiedMemData);
317 handleError();
318 }
319
320 return fault;
321}
322
323Addr
324CheckerCPU::dbg_vtophys(Addr addr)
325{
326 return vtophys(tc, addr);
327}
328
329/**
330 * Checks if the flags set by the Checker and Checkee match.
331 */
332bool
333CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
334 Addr pAddr, int flags)
335{
336 Addr unverifiedVAddr = unverified_req->getVaddr();
337 Addr unverifiedPAddr = unverified_req->getPaddr();
338 int unverifiedFlags = unverified_req->getFlags();
339
340 if (unverifiedVAddr != vAddr ||
341 unverifiedPAddr != pAddr ||
342 unverifiedFlags != flags) {
343 return false;
344 }
345
346 return true;
347}
348
349void
350CheckerCPU::dumpAndExit()
351{
352 warn("%lli: Checker PC:%s",
353 curTick(), thread->pcState());
354 panic("Checker found an error!");
355}
|