1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{
|
| 63 masterId = systemPtr->getMasterId(name());
|
63}
64
65CheckerCPU::CheckerCPU(Params *p)
66 : BaseCPU(p), thread(NULL), tc(NULL)
67{
68 memReq = NULL;
69 curStaticInst = NULL;
70 curMacroStaticInst = NULL;
71
72 numInst = 0;
73 startNumInst = 0;
74 numLoad = 0;
75 startNumLoad = 0;
76 youngestSN = 0;
77
78 changedPC = willChangePC = changedNextPC = false;
79
80 exitOnError = p->exitOnError;
81 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
82 itb = p->itb;
83 dtb = p->dtb;
84 systemPtr = NULL;
85 workload = p->workload;
86 // XXX: This is a hack to get this to work some
87 thread = new SimpleThread(this, /* thread_num */ 0,
88 workload.size() ? workload[0] : NULL, itb, dtb);
89
90 tc = thread->getTC();
91 threadContexts.push_back(tc);
92
93 updateOnError = true;
94}
95
96CheckerCPU::~CheckerCPU()
97{
98}
99
100void
101CheckerCPU::setSystem(System *system)
102{
103 systemPtr = system;
104
105 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
106
107 tc = thread->getTC();
108 threadContexts.push_back(tc);
109 delete thread->kernelStats;
110 thread->kernelStats = NULL;
111}
112
113void
114CheckerCPU::setIcachePort(Port *icache_port)
115{
116 icachePort = icache_port;
117}
118
119void
120CheckerCPU::setDcachePort(Port *dcache_port)
121{
122 dcachePort = dcache_port;
123}
124
125void
126CheckerCPU::serialize(ostream &os)
127{
128}
129
130void
131CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
132{
133}
134
135Fault
136CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
137{
138 Fault fault = NoFault;
139 unsigned blockSize = dcachePort->peerBlockSize();
140 int fullSize = size;
141 Addr secondAddr = roundDown(addr + size - 1, blockSize);
142 bool checked_flags = false;
143 bool flags_match = true;
144 Addr pAddr = 0x0;
145
146
147 if (secondAddr > addr)
148 size = secondAddr - addr;
149
150 // Need to account for multiple accesses like the Atomic and TimingSimple
151 while (1) {
152 memReq = new Request();
153 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
154
155 // translate to physical address
156 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
157
158 if (!checked_flags && fault == NoFault && unverifiedReq) {
159 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
160 memReq->getPaddr(), memReq->getFlags());
161 pAddr = memReq->getPaddr();
162 checked_flags = true;
163 }
164
165 // Now do the access
166 if (fault == NoFault &&
167 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
168 PacketPtr pkt = new Packet(memReq,
169 memReq->isLLSC() ?
170 MemCmd::LoadLockedReq : MemCmd::ReadReq,
171 Packet::Broadcast);
172
173 pkt->dataStatic(data);
174
175 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
176 // Access memory to see if we have the same data
177 dcachePort->sendFunctional(pkt);
178 } else {
179 // Assume the data is correct if it's an uncached access
180 memcpy(data, unverifiedMemData, size);
181 }
182
183 delete memReq;
184 memReq = NULL;
185 delete pkt;
186 }
187
188 if (fault != NoFault) {
189 if (memReq->isPrefetch()) {
190 fault = NoFault;
191 }
192 delete memReq;
193 memReq = NULL;
194 break;
195 }
196
197 if (memReq != NULL) {
198 delete memReq;
199 }
200
201 //If we don't need to access a second cache line, stop now.
202 if (secondAddr <= addr)
203 {
204 break;
205 }
206
207 // Setup for accessing next cache line
208 data += size;
209 unverifiedMemData += size;
210 size = addr + fullSize - secondAddr;
211 addr = secondAddr;
212 }
213
214 if (!flags_match) {
215 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
216 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
217 unverifiedReq->getFlags(), addr, pAddr, flags);
218 handleError();
219 }
220
221 return fault;
222}
223
224Fault
225CheckerCPU::writeMem(uint8_t *data, unsigned size,
226 Addr addr, unsigned flags, uint64_t *res)
227{
228 Fault fault = NoFault;
229 bool checked_flags = false;
230 bool flags_match = true;
231 Addr pAddr = 0x0;
232
233 unsigned blockSize = dcachePort->peerBlockSize();
234 int fullSize = size;
235
236 Addr secondAddr = roundDown(addr + size - 1, blockSize);
237
238 if (secondAddr > addr)
239 size = secondAddr - addr;
240
241 // Need to account for a multiple access like Atomic and Timing CPUs
242 while (1) {
243 memReq = new Request();
| 64}
65
66CheckerCPU::CheckerCPU(Params *p)
67 : BaseCPU(p), thread(NULL), tc(NULL)
68{
69 memReq = NULL;
70 curStaticInst = NULL;
71 curMacroStaticInst = NULL;
72
73 numInst = 0;
74 startNumInst = 0;
75 numLoad = 0;
76 startNumLoad = 0;
77 youngestSN = 0;
78
79 changedPC = willChangePC = changedNextPC = false;
80
81 exitOnError = p->exitOnError;
82 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
83 itb = p->itb;
84 dtb = p->dtb;
85 systemPtr = NULL;
86 workload = p->workload;
87 // XXX: This is a hack to get this to work some
88 thread = new SimpleThread(this, /* thread_num */ 0,
89 workload.size() ? workload[0] : NULL, itb, dtb);
90
91 tc = thread->getTC();
92 threadContexts.push_back(tc);
93
94 updateOnError = true;
95}
96
97CheckerCPU::~CheckerCPU()
98{
99}
100
101void
102CheckerCPU::setSystem(System *system)
103{
104 systemPtr = system;
105
106 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
107
108 tc = thread->getTC();
109 threadContexts.push_back(tc);
110 delete thread->kernelStats;
111 thread->kernelStats = NULL;
112}
113
114void
115CheckerCPU::setIcachePort(Port *icache_port)
116{
117 icachePort = icache_port;
118}
119
120void
121CheckerCPU::setDcachePort(Port *dcache_port)
122{
123 dcachePort = dcache_port;
124}
125
126void
127CheckerCPU::serialize(ostream &os)
128{
129}
130
131void
132CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
133{
134}
135
136Fault
137CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
138{
139 Fault fault = NoFault;
140 unsigned blockSize = dcachePort->peerBlockSize();
141 int fullSize = size;
142 Addr secondAddr = roundDown(addr + size - 1, blockSize);
143 bool checked_flags = false;
144 bool flags_match = true;
145 Addr pAddr = 0x0;
146
147
148 if (secondAddr > addr)
149 size = secondAddr - addr;
150
151 // Need to account for multiple accesses like the Atomic and TimingSimple
152 while (1) {
153 memReq = new Request();
154 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
155
156 // translate to physical address
157 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
158
159 if (!checked_flags && fault == NoFault && unverifiedReq) {
160 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
161 memReq->getPaddr(), memReq->getFlags());
162 pAddr = memReq->getPaddr();
163 checked_flags = true;
164 }
165
166 // Now do the access
167 if (fault == NoFault &&
168 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
169 PacketPtr pkt = new Packet(memReq,
170 memReq->isLLSC() ?
171 MemCmd::LoadLockedReq : MemCmd::ReadReq,
172 Packet::Broadcast);
173
174 pkt->dataStatic(data);
175
176 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
177 // Access memory to see if we have the same data
178 dcachePort->sendFunctional(pkt);
179 } else {
180 // Assume the data is correct if it's an uncached access
181 memcpy(data, unverifiedMemData, size);
182 }
183
184 delete memReq;
185 memReq = NULL;
186 delete pkt;
187 }
188
189 if (fault != NoFault) {
190 if (memReq->isPrefetch()) {
191 fault = NoFault;
192 }
193 delete memReq;
194 memReq = NULL;
195 break;
196 }
197
198 if (memReq != NULL) {
199 delete memReq;
200 }
201
202 //If we don't need to access a second cache line, stop now.
203 if (secondAddr <= addr)
204 {
205 break;
206 }
207
208 // Setup for accessing next cache line
209 data += size;
210 unverifiedMemData += size;
211 size = addr + fullSize - secondAddr;
212 addr = secondAddr;
213 }
214
215 if (!flags_match) {
216 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
217 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
218 unverifiedReq->getFlags(), addr, pAddr, flags);
219 handleError();
220 }
221
222 return fault;
223}
224
225Fault
226CheckerCPU::writeMem(uint8_t *data, unsigned size,
227 Addr addr, unsigned flags, uint64_t *res)
228{
229 Fault fault = NoFault;
230 bool checked_flags = false;
231 bool flags_match = true;
232 Addr pAddr = 0x0;
233
234 unsigned blockSize = dcachePort->peerBlockSize();
235 int fullSize = size;
236
237 Addr secondAddr = roundDown(addr + size - 1, blockSize);
238
239 if (secondAddr > addr)
240 size = secondAddr - addr;
241
242 // Need to account for a multiple access like Atomic and Timing CPUs
243 while (1) {
244 memReq = new Request();
|
244 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
| 245 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
|
245
246 // translate to physical address
247 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
248
249 if (!checked_flags && fault == NoFault && unverifiedReq) {
250 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
251 memReq->getPaddr(), memReq->getFlags());
252 pAddr = memReq->getPaddr();
253 checked_flags = true;
254 }
255
256 /*
257 * We don't actually check memory for the store because there
258 * is no guarantee it has left the lsq yet, and therefore we
259 * can't verify the memory on stores without lsq snooping
260 * enabled. This is left as future work for the Checker: LSQ snooping
261 * and memory validation after stores have committed.
262 */
263
264 delete memReq;
265
266 //If we don't need to access a second cache line, stop now.
267 if (fault != NoFault || secondAddr <= addr)
268 {
269 if (fault != NoFault && memReq->isPrefetch()) {
270 fault = NoFault;
271 }
272 break;
273 }
274
275 //Update size and access address
276 size = addr + fullSize - secondAddr;
277 //And access the right address.
278 addr = secondAddr;
279 }
280
281 if (!flags_match) {
282 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
283 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
284 unverifiedReq->getFlags(), addr, pAddr, flags);
285 handleError();
286 }
287
288 // Assume the result was the same as the one passed in. This checker
289 // doesn't check if the SC should succeed or fail, it just checks the
290 // value.
291 if (unverifiedReq && res && unverifiedReq->extraDataValid())
292 *res = unverifiedReq->getExtraData();
293
294 // Entire purpose here is to make sure we are getting the
295 // same data to send to the mem system as the CPU did.
296 // Cannot check this is actually what went to memory because
297 // there stores can be in ld/st queue or coherent operations
298 // overwriting values.
299 bool extraData;
300 if (unverifiedReq) {
301 extraData = unverifiedReq->extraDataValid() ?
302 unverifiedReq->getExtraData() : 1;
303 }
304
305 if (unverifiedReq && unverifiedMemData &&
306 memcmp(data, unverifiedMemData, fullSize) && extraData) {
307 warn("%lli: Store value does not match value sent to memory!\
308 data: %#x inst_data: %#x", curTick(), data,
309 unverifiedMemData);
310 handleError();
311 }
312
313 return fault;
314}
315
316Addr
317CheckerCPU::dbg_vtophys(Addr addr)
318{
319 return vtophys(tc, addr);
320}
321
322/**
323 * Checks if the flags set by the Checker and Checkee match.
324 */
325bool
326CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
327 Addr pAddr, int flags)
328{
329 Addr unverifiedVAddr = unverified_req->getVaddr();
330 Addr unverifiedPAddr = unverified_req->getPaddr();
331 int unverifiedFlags = unverified_req->getFlags();
332
333 if (unverifiedVAddr != vAddr ||
334 unverifiedPAddr != pAddr ||
335 unverifiedFlags != flags) {
336 return false;
337 }
338
339 return true;
340}
341
342void
343CheckerCPU::dumpAndExit()
344{
345 warn("%lli: Checker PC:%s",
346 curTick(), thread->pcState());
347 panic("Checker found an error!");
348}
| 246
247 // translate to physical address
248 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
249
250 if (!checked_flags && fault == NoFault && unverifiedReq) {
251 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
252 memReq->getPaddr(), memReq->getFlags());
253 pAddr = memReq->getPaddr();
254 checked_flags = true;
255 }
256
257 /*
258 * We don't actually check memory for the store because there
259 * is no guarantee it has left the lsq yet, and therefore we
260 * can't verify the memory on stores without lsq snooping
261 * enabled. This is left as future work for the Checker: LSQ snooping
262 * and memory validation after stores have committed.
263 */
264
265 delete memReq;
266
267 //If we don't need to access a second cache line, stop now.
268 if (fault != NoFault || secondAddr <= addr)
269 {
270 if (fault != NoFault && memReq->isPrefetch()) {
271 fault = NoFault;
272 }
273 break;
274 }
275
276 //Update size and access address
277 size = addr + fullSize - secondAddr;
278 //And access the right address.
279 addr = secondAddr;
280 }
281
282 if (!flags_match) {
283 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
284 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
285 unverifiedReq->getFlags(), addr, pAddr, flags);
286 handleError();
287 }
288
289 // Assume the result was the same as the one passed in. This checker
290 // doesn't check if the SC should succeed or fail, it just checks the
291 // value.
292 if (unverifiedReq && res && unverifiedReq->extraDataValid())
293 *res = unverifiedReq->getExtraData();
294
295 // Entire purpose here is to make sure we are getting the
296 // same data to send to the mem system as the CPU did.
297 // Cannot check this is actually what went to memory because
298 // there stores can be in ld/st queue or coherent operations
299 // overwriting values.
300 bool extraData;
301 if (unverifiedReq) {
302 extraData = unverifiedReq->extraDataValid() ?
303 unverifiedReq->getExtraData() : 1;
304 }
305
306 if (unverifiedReq && unverifiedMemData &&
307 memcmp(data, unverifiedMemData, fullSize) && extraData) {
308 warn("%lli: Store value does not match value sent to memory!\
309 data: %#x inst_data: %#x", curTick(), data,
310 unverifiedMemData);
311 handleError();
312 }
313
314 return fault;
315}
316
317Addr
318CheckerCPU::dbg_vtophys(Addr addr)
319{
320 return vtophys(tc, addr);
321}
322
323/**
324 * Checks if the flags set by the Checker and Checkee match.
325 */
326bool
327CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
328 Addr pAddr, int flags)
329{
330 Addr unverifiedVAddr = unverified_req->getVaddr();
331 Addr unverifiedPAddr = unverified_req->getPaddr();
332 int unverifiedFlags = unverified_req->getFlags();
333
334 if (unverifiedVAddr != vAddr ||
335 unverifiedPAddr != pAddr ||
336 unverifiedFlags != flags) {
337 return false;
338 }
339
340 return true;
341}
342
343void
344CheckerCPU::dumpAndExit()
345{
346 warn("%lli: Checker PC:%s",
347 curTick(), thread->pcState());
348 panic("Checker found an error!");
349}
|