3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include "cpu/checker/cpu.hh"
45
46#include <list>
47#include <string>
48
49#include "arch/generic/tlb.hh"
50#include "arch/kernel_stats.hh"
51#include "arch/vtophys.hh"
52#include "cpu/base.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56#include "params/CheckerCPU.hh"
57#include "sim/full_system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62void
63CheckerCPU::init()
64{
65 masterId = systemPtr->getMasterId(name());
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
72 memReq = NULL;
73 curStaticInst = NULL;
74 curMacroStaticInst = NULL;
75
76 numInst = 0;
77 startNumInst = 0;
78 numLoad = 0;
79 startNumLoad = 0;
80 youngestSN = 0;
81
82 changedPC = willChangePC = false;
83
84 exitOnError = p->exitOnError;
85 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
86 itb = p->itb;
87 dtb = p->dtb;
88 workload = p->workload;
89
90 updateOnError = true;
91}
92
93CheckerCPU::~CheckerCPU()
94{
95}
96
97void
98CheckerCPU::setSystem(System *system)
99{
100 const Params *p(dynamic_cast<const Params *>(_params));
101
102 systemPtr = system;
103
104 if (FullSystem) {
105 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
106 p->isa[0], false);
107 } else {
108 thread = new SimpleThread(this, 0, systemPtr,
109 workload.size() ? workload[0] : NULL,
110 itb, dtb, p->isa[0]);
111 }
112
113 tc = thread->getTC();
114 threadContexts.push_back(tc);
115 thread->kernelStats = NULL;
116 // Thread should never be null after this
117 assert(thread != NULL);
118}
119
120void
121CheckerCPU::setIcachePort(MasterPort *icache_port)
122{
123 icachePort = icache_port;
124}
125
126void
127CheckerCPU::setDcachePort(MasterPort *dcache_port)
128{
129 dcachePort = dcache_port;
130}
131
132void
133CheckerCPU::serialize(ostream &os) const
134{
135}
136
137void
138CheckerCPU::unserialize(CheckpointIn &cp)
139{
140}
141
142Fault
143CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
144 Request::Flags flags)
145{
146 Fault fault = NoFault;
147 int fullSize = size;
148 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
149 bool checked_flags = false;
150 bool flags_match = true;
151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 memReq = new Request(0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(memReq);
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
187 delete memReq;
188 memReq = NULL;
189 delete pkt;
190 }
191
192 if (fault != NoFault) {
193 if (memReq->isPrefetch()) {
194 fault = NoFault;
195 }
196 delete memReq;
197 memReq = NULL;
198 break;
199 }
200
201 if (memReq != NULL) {
202 delete memReq;
203 }
204
205 //If we don't need to access a second cache line, stop now.
206 if (secondAddr <= addr)
207 {
208 break;
209 }
210
211 // Setup for accessing next cache line
212 data += size;
213 unverifiedMemData += size;
214 size = addr + fullSize - secondAddr;
215 addr = secondAddr;
216 }
217
218 if (!flags_match) {
219 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
220 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
221 unverifiedReq->getFlags(), addr, pAddr, flags);
222 handleError();
223 }
224
225 return fault;
226}
227
228Fault
229CheckerCPU::writeMem(uint8_t *data, unsigned size,
230 Addr addr, Request::Flags flags, uint64_t *res)
231{
232 Fault fault = NoFault;
233 bool checked_flags = false;
234 bool flags_match = true;
235 Addr pAddr = 0x0;
236 static uint8_t zero_data[64] = {};
237
238 int fullSize = size;
239
240 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
241
242 if (secondAddr > addr)
243 size = secondAddr - addr;
244
245 // Need to account for a multiple access like Atomic and Timing CPUs
246 while (1) {
247 memReq = new Request(0, addr, size, flags, masterId,
248 thread->pcState().instAddr(), tc->contextId());
249
250 // translate to physical address
251 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
252
253 if (!checked_flags && fault == NoFault && unverifiedReq) {
254 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
255 memReq->getPaddr(), memReq->getFlags());
256 pAddr = memReq->getPaddr();
257 checked_flags = true;
258 }
259
260 /*
261 * We don't actually check memory for the store because there
262 * is no guarantee it has left the lsq yet, and therefore we
263 * can't verify the memory on stores without lsq snooping
264 * enabled. This is left as future work for the Checker: LSQ snooping
265 * and memory validation after stores have committed.
266 */
267 bool was_prefetch = memReq->isPrefetch();
268
269 delete memReq;
270
271 //If we don't need to access a second cache line, stop now.
272 if (fault != NoFault || secondAddr <= addr)
273 {
274 if (fault != NoFault && was_prefetch) {
275 fault = NoFault;
276 }
277 break;
278 }
279
280 //Update size and access address
281 size = addr + fullSize - secondAddr;
282 //And access the right address.
283 addr = secondAddr;
284 }
285
286 if (!flags_match) {
287 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
288 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
289 unverifiedReq->getFlags(), addr, pAddr, flags);
290 handleError();
291 }
292
293 // Assume the result was the same as the one passed in. This checker
294 // doesn't check if the SC should succeed or fail, it just checks the
295 // value.
296 if (unverifiedReq && res && unverifiedReq->extraDataValid())
297 *res = unverifiedReq->getExtraData();
298
299 // Entire purpose here is to make sure we are getting the
300 // same data to send to the mem system as the CPU did.
301 // Cannot check this is actually what went to memory because
302 // there stores can be in ld/st queue or coherent operations
303 // overwriting values.
304 bool extraData = false;
305 if (unverifiedReq) {
306 extraData = unverifiedReq->extraDataValid() ?
307 unverifiedReq->getExtraData() : true;
308 }
309
310 // If the request is to ZERO a cache block, there is no data to check
311 // against, but it's all zero. We need something to compare to, so use a
312 // const set of zeros.
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include "cpu/checker/cpu.hh"
45
46#include <list>
47#include <string>
48
49#include "arch/generic/tlb.hh"
50#include "arch/kernel_stats.hh"
51#include "arch/vtophys.hh"
52#include "cpu/base.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56#include "params/CheckerCPU.hh"
57#include "sim/full_system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62void
63CheckerCPU::init()
64{
65 masterId = systemPtr->getMasterId(name());
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
72 memReq = NULL;
73 curStaticInst = NULL;
74 curMacroStaticInst = NULL;
75
76 numInst = 0;
77 startNumInst = 0;
78 numLoad = 0;
79 startNumLoad = 0;
80 youngestSN = 0;
81
82 changedPC = willChangePC = false;
83
84 exitOnError = p->exitOnError;
85 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
86 itb = p->itb;
87 dtb = p->dtb;
88 workload = p->workload;
89
90 updateOnError = true;
91}
92
93CheckerCPU::~CheckerCPU()
94{
95}
96
97void
98CheckerCPU::setSystem(System *system)
99{
100 const Params *p(dynamic_cast<const Params *>(_params));
101
102 systemPtr = system;
103
104 if (FullSystem) {
105 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
106 p->isa[0], false);
107 } else {
108 thread = new SimpleThread(this, 0, systemPtr,
109 workload.size() ? workload[0] : NULL,
110 itb, dtb, p->isa[0]);
111 }
112
113 tc = thread->getTC();
114 threadContexts.push_back(tc);
115 thread->kernelStats = NULL;
116 // Thread should never be null after this
117 assert(thread != NULL);
118}
119
120void
121CheckerCPU::setIcachePort(MasterPort *icache_port)
122{
123 icachePort = icache_port;
124}
125
126void
127CheckerCPU::setDcachePort(MasterPort *dcache_port)
128{
129 dcachePort = dcache_port;
130}
131
132void
133CheckerCPU::serialize(ostream &os) const
134{
135}
136
137void
138CheckerCPU::unserialize(CheckpointIn &cp)
139{
140}
141
142Fault
143CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
144 Request::Flags flags)
145{
146 Fault fault = NoFault;
147 int fullSize = size;
148 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
149 bool checked_flags = false;
150 bool flags_match = true;
151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 memReq = new Request(0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(memReq);
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
187 delete memReq;
188 memReq = NULL;
189 delete pkt;
190 }
191
192 if (fault != NoFault) {
193 if (memReq->isPrefetch()) {
194 fault = NoFault;
195 }
196 delete memReq;
197 memReq = NULL;
198 break;
199 }
200
201 if (memReq != NULL) {
202 delete memReq;
203 }
204
205 //If we don't need to access a second cache line, stop now.
206 if (secondAddr <= addr)
207 {
208 break;
209 }
210
211 // Setup for accessing next cache line
212 data += size;
213 unverifiedMemData += size;
214 size = addr + fullSize - secondAddr;
215 addr = secondAddr;
216 }
217
218 if (!flags_match) {
219 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
220 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
221 unverifiedReq->getFlags(), addr, pAddr, flags);
222 handleError();
223 }
224
225 return fault;
226}
227
228Fault
229CheckerCPU::writeMem(uint8_t *data, unsigned size,
230 Addr addr, Request::Flags flags, uint64_t *res)
231{
232 Fault fault = NoFault;
233 bool checked_flags = false;
234 bool flags_match = true;
235 Addr pAddr = 0x0;
236 static uint8_t zero_data[64] = {};
237
238 int fullSize = size;
239
240 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
241
242 if (secondAddr > addr)
243 size = secondAddr - addr;
244
245 // Need to account for a multiple access like Atomic and Timing CPUs
246 while (1) {
247 memReq = new Request(0, addr, size, flags, masterId,
248 thread->pcState().instAddr(), tc->contextId());
249
250 // translate to physical address
251 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
252
253 if (!checked_flags && fault == NoFault && unverifiedReq) {
254 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
255 memReq->getPaddr(), memReq->getFlags());
256 pAddr = memReq->getPaddr();
257 checked_flags = true;
258 }
259
260 /*
261 * We don't actually check memory for the store because there
262 * is no guarantee it has left the lsq yet, and therefore we
263 * can't verify the memory on stores without lsq snooping
264 * enabled. This is left as future work for the Checker: LSQ snooping
265 * and memory validation after stores have committed.
266 */
267 bool was_prefetch = memReq->isPrefetch();
268
269 delete memReq;
270
271 //If we don't need to access a second cache line, stop now.
272 if (fault != NoFault || secondAddr <= addr)
273 {
274 if (fault != NoFault && was_prefetch) {
275 fault = NoFault;
276 }
277 break;
278 }
279
280 //Update size and access address
281 size = addr + fullSize - secondAddr;
282 //And access the right address.
283 addr = secondAddr;
284 }
285
286 if (!flags_match) {
287 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
288 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
289 unverifiedReq->getFlags(), addr, pAddr, flags);
290 handleError();
291 }
292
293 // Assume the result was the same as the one passed in. This checker
294 // doesn't check if the SC should succeed or fail, it just checks the
295 // value.
296 if (unverifiedReq && res && unverifiedReq->extraDataValid())
297 *res = unverifiedReq->getExtraData();
298
299 // Entire purpose here is to make sure we are getting the
300 // same data to send to the mem system as the CPU did.
301 // Cannot check this is actually what went to memory because
302 // there stores can be in ld/st queue or coherent operations
303 // overwriting values.
304 bool extraData = false;
305 if (unverifiedReq) {
306 extraData = unverifiedReq->extraDataValid() ?
307 unverifiedReq->getExtraData() : true;
308 }
309
310 // If the request is to ZERO a cache block, there is no data to check
311 // against, but it's all zero. We need something to compare to, so use a
312 // const set of zeros.
|