1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
| 1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
|
51#include "cpu/base.hh"
52#include "cpu/simple_thread.hh"
53#include "cpu/static_inst.hh"
54#include "cpu/thread_context.hh"
55#include "params/CheckerCPU.hh"
56#include "sim/full_system.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{
64 masterId = systemPtr->getMasterId(name());
65}
66
67CheckerCPU::CheckerCPU(Params *p)
68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69 tc(NULL), thread(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87 workload = p->workload;
88
89 updateOnError = true;
90}
91
92CheckerCPU::~CheckerCPU()
93{
94}
95
96void
97CheckerCPU::setSystem(System *system)
98{
99 const Params *p(dynamic_cast<const Params *>(_params));
100
101 systemPtr = system;
102
103 if (FullSystem) {
104 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
105 p->isa[0], false);
106 } else {
107 thread = new SimpleThread(this, 0, systemPtr,
108 workload.size() ? workload[0] : NULL,
109 itb, dtb, p->isa[0]);
110 }
111
112 tc = thread->getTC();
113 threadContexts.push_back(tc);
114 thread->kernelStats = NULL;
115 // Thread should never be null after this
116 assert(thread != NULL);
117}
118
119void
120CheckerCPU::setIcachePort(MasterPort *icache_port)
121{
122 icachePort = icache_port;
123}
124
125void
126CheckerCPU::setDcachePort(MasterPort *dcache_port)
127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os) const
133{
134}
135
136void
137CheckerCPU::unserialize(CheckpointIn &cp)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
143 Request::Flags flags)
144{
145 Fault fault = NoFault;
146 int fullSize = size;
147 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
148 bool checked_flags = false;
149 bool flags_match = true;
150 Addr pAddr = 0x0;
151
152
153 if (secondAddr > addr)
154 size = secondAddr - addr;
155
156 // Need to account for multiple accesses like the Atomic and TimingSimple
157 while (1) {
158 memReq = new Request(0, addr, size, flags, masterId,
159 thread->pcState().instAddr(), tc->contextId());
160
161 // translate to physical address
162 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
163
164 if (!checked_flags && fault == NoFault && unverifiedReq) {
165 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
166 memReq->getPaddr(), memReq->getFlags());
167 pAddr = memReq->getPaddr();
168 checked_flags = true;
169 }
170
171 // Now do the access
172 if (fault == NoFault &&
173 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
174 PacketPtr pkt = Packet::createRead(memReq);
175
176 pkt->dataStatic(data);
177
178 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
179 // Access memory to see if we have the same data
180 dcachePort->sendFunctional(pkt);
181 } else {
182 // Assume the data is correct if it's an uncached access
183 memcpy(data, unverifiedMemData, size);
184 }
185
186 delete memReq;
187 memReq = NULL;
188 delete pkt;
189 }
190
191 if (fault != NoFault) {
192 if (memReq->isPrefetch()) {
193 fault = NoFault;
194 }
195 delete memReq;
196 memReq = NULL;
197 break;
198 }
199
200 if (memReq != NULL) {
201 delete memReq;
202 }
203
204 //If we don't need to access a second cache line, stop now.
205 if (secondAddr <= addr)
206 {
207 break;
208 }
209
210 // Setup for accessing next cache line
211 data += size;
212 unverifiedMemData += size;
213 size = addr + fullSize - secondAddr;
214 addr = secondAddr;
215 }
216
217 if (!flags_match) {
218 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
219 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
220 unverifiedReq->getFlags(), addr, pAddr, flags);
221 handleError();
222 }
223
224 return fault;
225}
226
227Fault
228CheckerCPU::writeMem(uint8_t *data, unsigned size,
229 Addr addr, Request::Flags flags, uint64_t *res)
230{
231 Fault fault = NoFault;
232 bool checked_flags = false;
233 bool flags_match = true;
234 Addr pAddr = 0x0;
235 static uint8_t zero_data[64] = {};
236
237 int fullSize = size;
238
239 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
240
241 if (secondAddr > addr)
242 size = secondAddr - addr;
243
244 // Need to account for a multiple access like Atomic and Timing CPUs
245 while (1) {
246 memReq = new Request(0, addr, size, flags, masterId,
247 thread->pcState().instAddr(), tc->contextId());
248
249 // translate to physical address
250 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
251
252 if (!checked_flags && fault == NoFault && unverifiedReq) {
253 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
254 memReq->getPaddr(), memReq->getFlags());
255 pAddr = memReq->getPaddr();
256 checked_flags = true;
257 }
258
259 /*
260 * We don't actually check memory for the store because there
261 * is no guarantee it has left the lsq yet, and therefore we
262 * can't verify the memory on stores without lsq snooping
263 * enabled. This is left as future work for the Checker: LSQ snooping
264 * and memory validation after stores have committed.
265 */
266 bool was_prefetch = memReq->isPrefetch();
267
268 delete memReq;
269
270 //If we don't need to access a second cache line, stop now.
271 if (fault != NoFault || secondAddr <= addr)
272 {
273 if (fault != NoFault && was_prefetch) {
274 fault = NoFault;
275 }
276 break;
277 }
278
279 //Update size and access address
280 size = addr + fullSize - secondAddr;
281 //And access the right address.
282 addr = secondAddr;
283 }
284
285 if (!flags_match) {
286 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
287 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
288 unverifiedReq->getFlags(), addr, pAddr, flags);
289 handleError();
290 }
291
292 // Assume the result was the same as the one passed in. This checker
293 // doesn't check if the SC should succeed or fail, it just checks the
294 // value.
295 if (unverifiedReq && res && unverifiedReq->extraDataValid())
296 *res = unverifiedReq->getExtraData();
297
298 // Entire purpose here is to make sure we are getting the
299 // same data to send to the mem system as the CPU did.
300 // Cannot check this is actually what went to memory because
301 // there stores can be in ld/st queue or coherent operations
302 // overwriting values.
303 bool extraData = false;
304 if (unverifiedReq) {
305 extraData = unverifiedReq->extraDataValid() ?
306 unverifiedReq->getExtraData() : true;
307 }
308
309 // If the request is to ZERO a cache block, there is no data to check
310 // against, but it's all zero. We need something to compare to, so use a
311 // const set of zeros.
312 if (flags & Request::CACHE_BLOCK_ZERO) {
313 assert(!data);
314 assert(sizeof(zero_data) <= fullSize);
315 data = zero_data;
316 }
317
318 if (unverifiedReq && unverifiedMemData &&
319 memcmp(data, unverifiedMemData, fullSize) && extraData) {
320 warn("%lli: Store value does not match value sent to memory! "
321 "data: %#x inst_data: %#x", curTick(), data,
322 unverifiedMemData);
323 handleError();
324 }
325
326 return fault;
327}
328
329Addr
330CheckerCPU::dbg_vtophys(Addr addr)
331{
332 return vtophys(tc, addr);
333}
334
335/**
336 * Checks if the flags set by the Checker and Checkee match.
337 */
338bool
339CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
340 Addr pAddr, int flags)
341{
342 Addr unverifiedVAddr = unverified_req->getVaddr();
343 Addr unverifiedPAddr = unverified_req->getPaddr();
344 int unverifiedFlags = unverified_req->getFlags();
345
346 if (unverifiedVAddr != vAddr ||
347 unverifiedPAddr != pAddr ||
348 unverifiedFlags != flags) {
349 return false;
350 }
351
352 return true;
353}
354
355void
356CheckerCPU::dumpAndExit()
357{
358 warn("%lli: Checker PC:%s",
359 curTick(), thread->pcState());
360 panic("Checker found an error!");
361}
| 52#include "cpu/base.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56#include "params/CheckerCPU.hh"
57#include "sim/full_system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62void
63CheckerCPU::init()
64{
65 masterId = systemPtr->getMasterId(name());
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
72 memReq = NULL;
73 curStaticInst = NULL;
74 curMacroStaticInst = NULL;
75
76 numInst = 0;
77 startNumInst = 0;
78 numLoad = 0;
79 startNumLoad = 0;
80 youngestSN = 0;
81
82 changedPC = willChangePC = false;
83
84 exitOnError = p->exitOnError;
85 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
86 itb = p->itb;
87 dtb = p->dtb;
88 workload = p->workload;
89
90 updateOnError = true;
91}
92
93CheckerCPU::~CheckerCPU()
94{
95}
96
97void
98CheckerCPU::setSystem(System *system)
99{
100 const Params *p(dynamic_cast<const Params *>(_params));
101
102 systemPtr = system;
103
104 if (FullSystem) {
105 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
106 p->isa[0], false);
107 } else {
108 thread = new SimpleThread(this, 0, systemPtr,
109 workload.size() ? workload[0] : NULL,
110 itb, dtb, p->isa[0]);
111 }
112
113 tc = thread->getTC();
114 threadContexts.push_back(tc);
115 thread->kernelStats = NULL;
116 // Thread should never be null after this
117 assert(thread != NULL);
118}
119
120void
121CheckerCPU::setIcachePort(MasterPort *icache_port)
122{
123 icachePort = icache_port;
124}
125
126void
127CheckerCPU::setDcachePort(MasterPort *dcache_port)
128{
129 dcachePort = dcache_port;
130}
131
132void
133CheckerCPU::serialize(ostream &os) const
134{
135}
136
137void
138CheckerCPU::unserialize(CheckpointIn &cp)
139{
140}
141
142Fault
143CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
144 Request::Flags flags)
145{
146 Fault fault = NoFault;
147 int fullSize = size;
148 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
149 bool checked_flags = false;
150 bool flags_match = true;
151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 memReq = new Request(0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(memReq);
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
187 delete memReq;
188 memReq = NULL;
189 delete pkt;
190 }
191
192 if (fault != NoFault) {
193 if (memReq->isPrefetch()) {
194 fault = NoFault;
195 }
196 delete memReq;
197 memReq = NULL;
198 break;
199 }
200
201 if (memReq != NULL) {
202 delete memReq;
203 }
204
205 //If we don't need to access a second cache line, stop now.
206 if (secondAddr <= addr)
207 {
208 break;
209 }
210
211 // Setup for accessing next cache line
212 data += size;
213 unverifiedMemData += size;
214 size = addr + fullSize - secondAddr;
215 addr = secondAddr;
216 }
217
218 if (!flags_match) {
219 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
220 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
221 unverifiedReq->getFlags(), addr, pAddr, flags);
222 handleError();
223 }
224
225 return fault;
226}
227
228Fault
229CheckerCPU::writeMem(uint8_t *data, unsigned size,
230 Addr addr, Request::Flags flags, uint64_t *res)
231{
232 Fault fault = NoFault;
233 bool checked_flags = false;
234 bool flags_match = true;
235 Addr pAddr = 0x0;
236 static uint8_t zero_data[64] = {};
237
238 int fullSize = size;
239
240 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
241
242 if (secondAddr > addr)
243 size = secondAddr - addr;
244
245 // Need to account for a multiple access like Atomic and Timing CPUs
246 while (1) {
247 memReq = new Request(0, addr, size, flags, masterId,
248 thread->pcState().instAddr(), tc->contextId());
249
250 // translate to physical address
251 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
252
253 if (!checked_flags && fault == NoFault && unverifiedReq) {
254 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
255 memReq->getPaddr(), memReq->getFlags());
256 pAddr = memReq->getPaddr();
257 checked_flags = true;
258 }
259
260 /*
261 * We don't actually check memory for the store because there
262 * is no guarantee it has left the lsq yet, and therefore we
263 * can't verify the memory on stores without lsq snooping
264 * enabled. This is left as future work for the Checker: LSQ snooping
265 * and memory validation after stores have committed.
266 */
267 bool was_prefetch = memReq->isPrefetch();
268
269 delete memReq;
270
271 //If we don't need to access a second cache line, stop now.
272 if (fault != NoFault || secondAddr <= addr)
273 {
274 if (fault != NoFault && was_prefetch) {
275 fault = NoFault;
276 }
277 break;
278 }
279
280 //Update size and access address
281 size = addr + fullSize - secondAddr;
282 //And access the right address.
283 addr = secondAddr;
284 }
285
286 if (!flags_match) {
287 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
288 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
289 unverifiedReq->getFlags(), addr, pAddr, flags);
290 handleError();
291 }
292
293 // Assume the result was the same as the one passed in. This checker
294 // doesn't check if the SC should succeed or fail, it just checks the
295 // value.
296 if (unverifiedReq && res && unverifiedReq->extraDataValid())
297 *res = unverifiedReq->getExtraData();
298
299 // Entire purpose here is to make sure we are getting the
300 // same data to send to the mem system as the CPU did.
301 // Cannot check this is actually what went to memory because
302 // there stores can be in ld/st queue or coherent operations
303 // overwriting values.
304 bool extraData = false;
305 if (unverifiedReq) {
306 extraData = unverifiedReq->extraDataValid() ?
307 unverifiedReq->getExtraData() : true;
308 }
309
310 // If the request is to ZERO a cache block, there is no data to check
311 // against, but it's all zero. We need something to compare to, so use a
312 // const set of zeros.
313 if (flags & Request::CACHE_BLOCK_ZERO) {
314 assert(!data);
315 assert(sizeof(zero_data) <= fullSize);
316 data = zero_data;
317 }
318
319 if (unverifiedReq && unverifiedMemData &&
320 memcmp(data, unverifiedMemData, fullSize) && extraData) {
321 warn("%lli: Store value does not match value sent to memory! "
322 "data: %#x inst_data: %#x", curTick(), data,
323 unverifiedMemData);
324 handleError();
325 }
326
327 return fault;
328}
329
330Addr
331CheckerCPU::dbg_vtophys(Addr addr)
332{
333 return vtophys(tc, addr);
334}
335
336/**
337 * Checks if the flags set by the Checker and Checkee match.
338 */
339bool
340CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
341 Addr pAddr, int flags)
342{
343 Addr unverifiedVAddr = unverified_req->getVaddr();
344 Addr unverifiedPAddr = unverified_req->getPaddr();
345 int unverifiedFlags = unverified_req->getFlags();
346
347 if (unverifiedVAddr != vAddr ||
348 unverifiedPAddr != pAddr ||
349 unverifiedFlags != flags) {
350 return false;
351 }
352
353 return true;
354}
355
356void
357CheckerCPU::dumpAndExit()
358{
359 warn("%lli: Checker PC:%s",
360 curTick(), thread->pcState());
361 panic("Checker found an error!");
362}
|