1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/full_system.hh"
56#include "sim/tlb.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{
64 masterId = systemPtr->getMasterId(name());
65}
66
67CheckerCPU::CheckerCPU(Params *p)
68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69 tc(NULL), thread(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87 workload = p->workload;
88
89 updateOnError = true;
90}
91
92CheckerCPU::~CheckerCPU()
93{
94}
95
96void
97CheckerCPU::setSystem(System *system)
98{
99 const Params *p(dynamic_cast<const Params *>(_params));
100
101 systemPtr = system;
102
103 if (FullSystem) {
104 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
105 p->isa[0], false);
106 } else {
107 thread = new SimpleThread(this, 0, systemPtr,
108 workload.size() ? workload[0] : NULL,
109 itb, dtb, p->isa[0]);
110 }
111
112 tc = thread->getTC();
113 threadContexts.push_back(tc);
114 thread->kernelStats = NULL;
115 // Thread should never be null after this
116 assert(thread != NULL);
117}
118
119void
120CheckerCPU::setIcachePort(MasterPort *icache_port)
121{
122 icachePort = icache_port;
123}
124
125void
126CheckerCPU::setDcachePort(MasterPort *dcache_port)
127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os)
133{
134}
135
136void
137CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
143{
144 Fault fault = NoFault;
145 int fullSize = size;
146 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
147 bool checked_flags = false;
148 bool flags_match = true;
149 Addr pAddr = 0x0;
150
151
152 if (secondAddr > addr)
153 size = secondAddr - addr;
154
155 // Need to account for multiple accesses like the Atomic and TimingSimple
156 while (1) {
157 memReq = new Request();
158 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
159
160 // translate to physical address
161 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
162
163 if (!checked_flags && fault == NoFault && unverifiedReq) {
164 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
165 memReq->getPaddr(), memReq->getFlags());
166 pAddr = memReq->getPaddr();
167 checked_flags = true;
168 }
169
170 // Now do the access
171 if (fault == NoFault &&
172 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
173 PacketPtr pkt = Packet::createRead(memReq);
174
175 pkt->dataStatic(data);
176
177 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
178 // Access memory to see if we have the same data
179 dcachePort->sendFunctional(pkt);
180 } else {
181 // Assume the data is correct if it's an uncached access
182 memcpy(data, unverifiedMemData, size);
183 }
184
185 delete memReq;
186 memReq = NULL;
187 delete pkt;
188 }
189
190 if (fault != NoFault) {
191 if (memReq->isPrefetch()) {
192 fault = NoFault;
193 }
194 delete memReq;
195 memReq = NULL;
196 break;
197 }
198
199 if (memReq != NULL) {
200 delete memReq;
201 }
202
203 //If we don't need to access a second cache line, stop now.
204 if (secondAddr <= addr)
205 {
206 break;
207 }
208
209 // Setup for accessing next cache line
210 data += size;
211 unverifiedMemData += size;
212 size = addr + fullSize - secondAddr;
213 addr = secondAddr;
214 }
215
216 if (!flags_match) {
217 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
218 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
219 unverifiedReq->getFlags(), addr, pAddr, flags);
220 handleError();
221 }
222
223 return fault;
224}
225
226Fault
227CheckerCPU::writeMem(uint8_t *data, unsigned size,
228 Addr addr, unsigned flags, uint64_t *res)
229{
230 Fault fault = NoFault;
231 bool checked_flags = false;
232 bool flags_match = true;
233 Addr pAddr = 0x0;
234
235 int fullSize = size;
236
237 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
238
239 if (secondAddr > addr)
240 size = secondAddr - addr;
241
242 // Need to account for a multiple access like Atomic and Timing CPUs
243 while (1) {
244 memReq = new Request();
245 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
246
247 // translate to physical address
248 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
249
250 if (!checked_flags && fault == NoFault && unverifiedReq) {
251 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
252 memReq->getPaddr(), memReq->getFlags());
253 pAddr = memReq->getPaddr();
254 checked_flags = true;
255 }
256
257 /*
258 * We don't actually check memory for the store because there
259 * is no guarantee it has left the lsq yet, and therefore we
260 * can't verify the memory on stores without lsq snooping
261 * enabled. This is left as future work for the Checker: LSQ snooping
262 * and memory validation after stores have committed.
263 */
264 bool was_prefetch = memReq->isPrefetch();
265
266 delete memReq;
267
268 //If we don't need to access a second cache line, stop now.
269 if (fault != NoFault || secondAddr <= addr)
270 {
271 if (fault != NoFault && was_prefetch) {
272 fault = NoFault;
273 }
274 break;
275 }
276
277 //Update size and access address
278 size = addr + fullSize - secondAddr;
279 //And access the right address.
280 addr = secondAddr;
281 }
282
283 if (!flags_match) {
284 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
285 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
286 unverifiedReq->getFlags(), addr, pAddr, flags);
287 handleError();
288 }
289
290 // Assume the result was the same as the one passed in. This checker
291 // doesn't check if the SC should succeed or fail, it just checks the
292 // value.
293 if (unverifiedReq && res && unverifiedReq->extraDataValid())
294 *res = unverifiedReq->getExtraData();
295
296 // Entire purpose here is to make sure we are getting the
297 // same data to send to the mem system as the CPU did.
298 // Cannot check this is actually what went to memory because
299 // there stores can be in ld/st queue or coherent operations
300 // overwriting values.
| 1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "arch/kernel_stats.hh"
48#include "arch/vtophys.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/base.hh"
51#include "cpu/simple_thread.hh"
52#include "cpu/static_inst.hh"
53#include "cpu/thread_context.hh"
54#include "params/CheckerCPU.hh"
55#include "sim/full_system.hh"
56#include "sim/tlb.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()
63{
64 masterId = systemPtr->getMasterId(name());
65}
66
67CheckerCPU::CheckerCPU(Params *p)
68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
69 tc(NULL), thread(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87 workload = p->workload;
88
89 updateOnError = true;
90}
91
92CheckerCPU::~CheckerCPU()
93{
94}
95
96void
97CheckerCPU::setSystem(System *system)
98{
99 const Params *p(dynamic_cast<const Params *>(_params));
100
101 systemPtr = system;
102
103 if (FullSystem) {
104 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
105 p->isa[0], false);
106 } else {
107 thread = new SimpleThread(this, 0, systemPtr,
108 workload.size() ? workload[0] : NULL,
109 itb, dtb, p->isa[0]);
110 }
111
112 tc = thread->getTC();
113 threadContexts.push_back(tc);
114 thread->kernelStats = NULL;
115 // Thread should never be null after this
116 assert(thread != NULL);
117}
118
119void
120CheckerCPU::setIcachePort(MasterPort *icache_port)
121{
122 icachePort = icache_port;
123}
124
125void
126CheckerCPU::setDcachePort(MasterPort *dcache_port)
127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os)
133{
134}
135
136void
137CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
143{
144 Fault fault = NoFault;
145 int fullSize = size;
146 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
147 bool checked_flags = false;
148 bool flags_match = true;
149 Addr pAddr = 0x0;
150
151
152 if (secondAddr > addr)
153 size = secondAddr - addr;
154
155 // Need to account for multiple accesses like the Atomic and TimingSimple
156 while (1) {
157 memReq = new Request();
158 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
159
160 // translate to physical address
161 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
162
163 if (!checked_flags && fault == NoFault && unverifiedReq) {
164 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
165 memReq->getPaddr(), memReq->getFlags());
166 pAddr = memReq->getPaddr();
167 checked_flags = true;
168 }
169
170 // Now do the access
171 if (fault == NoFault &&
172 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
173 PacketPtr pkt = Packet::createRead(memReq);
174
175 pkt->dataStatic(data);
176
177 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
178 // Access memory to see if we have the same data
179 dcachePort->sendFunctional(pkt);
180 } else {
181 // Assume the data is correct if it's an uncached access
182 memcpy(data, unverifiedMemData, size);
183 }
184
185 delete memReq;
186 memReq = NULL;
187 delete pkt;
188 }
189
190 if (fault != NoFault) {
191 if (memReq->isPrefetch()) {
192 fault = NoFault;
193 }
194 delete memReq;
195 memReq = NULL;
196 break;
197 }
198
199 if (memReq != NULL) {
200 delete memReq;
201 }
202
203 //If we don't need to access a second cache line, stop now.
204 if (secondAddr <= addr)
205 {
206 break;
207 }
208
209 // Setup for accessing next cache line
210 data += size;
211 unverifiedMemData += size;
212 size = addr + fullSize - secondAddr;
213 addr = secondAddr;
214 }
215
216 if (!flags_match) {
217 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
218 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
219 unverifiedReq->getFlags(), addr, pAddr, flags);
220 handleError();
221 }
222
223 return fault;
224}
225
226Fault
227CheckerCPU::writeMem(uint8_t *data, unsigned size,
228 Addr addr, unsigned flags, uint64_t *res)
229{
230 Fault fault = NoFault;
231 bool checked_flags = false;
232 bool flags_match = true;
233 Addr pAddr = 0x0;
234
235 int fullSize = size;
236
237 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
238
239 if (secondAddr > addr)
240 size = secondAddr - addr;
241
242 // Need to account for a multiple access like Atomic and Timing CPUs
243 while (1) {
244 memReq = new Request();
245 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
246
247 // translate to physical address
248 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
249
250 if (!checked_flags && fault == NoFault && unverifiedReq) {
251 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
252 memReq->getPaddr(), memReq->getFlags());
253 pAddr = memReq->getPaddr();
254 checked_flags = true;
255 }
256
257 /*
258 * We don't actually check memory for the store because there
259 * is no guarantee it has left the lsq yet, and therefore we
260 * can't verify the memory on stores without lsq snooping
261 * enabled. This is left as future work for the Checker: LSQ snooping
262 * and memory validation after stores have committed.
263 */
264 bool was_prefetch = memReq->isPrefetch();
265
266 delete memReq;
267
268 //If we don't need to access a second cache line, stop now.
269 if (fault != NoFault || secondAddr <= addr)
270 {
271 if (fault != NoFault && was_prefetch) {
272 fault = NoFault;
273 }
274 break;
275 }
276
277 //Update size and access address
278 size = addr + fullSize - secondAddr;
279 //And access the right address.
280 addr = secondAddr;
281 }
282
283 if (!flags_match) {
284 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
285 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
286 unverifiedReq->getFlags(), addr, pAddr, flags);
287 handleError();
288 }
289
290 // Assume the result was the same as the one passed in. This checker
291 // doesn't check if the SC should succeed or fail, it just checks the
292 // value.
293 if (unverifiedReq && res && unverifiedReq->extraDataValid())
294 *res = unverifiedReq->getExtraData();
295
296 // Entire purpose here is to make sure we are getting the
297 // same data to send to the mem system as the CPU did.
298 // Cannot check this is actually what went to memory because
299 // there stores can be in ld/st queue or coherent operations
300 // overwriting values.
|