1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55#include "sim/tlb.hh"
56
57using namespace std;
58using namespace TheISA;
59
60void
61CheckerCPU::init()
62{
63}
64
65CheckerCPU::CheckerCPU(Params *p)
66 : BaseCPU(p), thread(NULL), tc(NULL)
67{
68 memReq = NULL;
69 curStaticInst = NULL;
70 curMacroStaticInst = NULL;

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236 Addr secondAddr = roundDown(addr + size - 1, blockSize);
237
238 if (secondAddr > addr)
239 size = secondAddr - addr;
240
241 // Need to account for a multiple access like Atomic and Timing CPUs
242 while (1) {
243 memReq = new Request();
244 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
245
246 // translate to physical address
247 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
248
249 if (!checked_flags && fault == NoFault && unverifiedReq) {
250 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
251 memReq->getPaddr(), memReq->getFlags());
252 pAddr = memReq->getPaddr();

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