1/*
2 * Copyright (c) 2011,2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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47#include <string>
48
49#include "arch/generic/tlb.hh"
50#include "arch/vtophys.hh"
51#include "cpu/base.hh"
52#include "cpu/simple_thread.hh"
53#include "cpu/static_inst.hh"
54#include "cpu/thread_context.hh"
55#include "params/CheckerCPU.hh"
56#include "sim/full_system.hh"
57
58using namespace std;
59using namespace TheISA;
60
61void
62CheckerCPU::init()

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134{
135}
136
137void
138CheckerCPU::unserialize(CheckpointIn &cp)
139{
140}
141
142Fault
143CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
144 Request::Flags flags)
145{
146 Fault fault = NoFault;
147 int fullSize = size;
148 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
149 bool checked_flags = false;
150 bool flags_match = true;
151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 auto mem_req = std::make_shared<Request>(
160 0, addr, size, flags, masterId,
161 thread->pcState().instAddr(), tc->contextId());
162
163 // translate to physical address
164 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
165
166 if (!checked_flags && fault == NoFault && unverifiedReq) {
167 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
168 mem_req->getPaddr(), mem_req->getFlags());
169 pAddr = mem_req->getPaddr();
170 checked_flags = true;
171 }
172
173 // Now do the access
174 if (fault == NoFault &&
175 !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
176 PacketPtr pkt = Packet::createRead(mem_req);
177
178 pkt->dataStatic(data);
179
180 if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
181 // Access memory to see if we have the same data
182 dcachePort->sendFunctional(pkt);
183 } else {
184 // Assume the data is correct if it's an uncached access
185 memcpy(data, unverifiedMemData, size);
186 }
187
188 delete pkt;
189 }
190
191 if (fault != NoFault) {
192 if (mem_req->isPrefetch()) {
193 fault = NoFault;
194 }
195 break;
196 }
197
198 //If we don't need to access a second cache line, stop now.
199 if (secondAddr <= addr)
200 {
201 break;
202 }
203
204 // Setup for accessing next cache line
205 data += size;
206 unverifiedMemData += size;
207 size = addr + fullSize - secondAddr;
208 addr = secondAddr;
209 }
210
211 if (!flags_match) {
212 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
213 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
214 unverifiedReq->getFlags(), addr, pAddr, flags);
215 handleError();
216 }
217
218 return fault;
219}
220
221Fault
222CheckerCPU::writeMem(uint8_t *data, unsigned size,
223 Addr addr, Request::Flags flags, uint64_t *res)
224{
225 Fault fault = NoFault;
226 bool checked_flags = false;
227 bool flags_match = true;
228 Addr pAddr = 0x0;
229 static uint8_t zero_data[64] = {};
230
231 int fullSize = size;
232
233 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
234
235 if (secondAddr > addr)
236 size = secondAddr - addr;
237
238 // Need to account for a multiple access like Atomic and Timing CPUs
239 while (1) {
240 auto mem_req = std::make_shared<Request>(
241 0, addr, size, flags, masterId,
242 thread->pcState().instAddr(), tc->contextId());
243
244 // translate to physical address
245 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
246
247 if (!checked_flags && fault == NoFault && unverifiedReq) {
248 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
249 mem_req->getPaddr(), mem_req->getFlags());
250 pAddr = mem_req->getPaddr();
251 checked_flags = true;
252 }
253
254 /*
255 * We don't actually check memory for the store because there
256 * is no guarantee it has left the lsq yet, and therefore we
257 * can't verify the memory on stores without lsq snooping
258 * enabled. This is left as future work for the Checker: LSQ snooping
259 * and memory validation after stores have committed.
260 */
261 bool was_prefetch = mem_req->isPrefetch();
262
263 //If we don't need to access a second cache line, stop now.
264 if (fault != NoFault || secondAddr <= addr)
265 {
266 if (fault != NoFault && was_prefetch) {
267 fault = NoFault;
268 }
269 break;
270 }
271
272 //Update size and access address
273 size = addr + fullSize - secondAddr;
274 //And access the right address.
275 addr = secondAddr;
276 }
277
278 if (!flags_match) {
279 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
280 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
281 unverifiedReq->getFlags(), addr, pAddr, flags);
282 handleError();
283 }
284
285 // Assume the result was the same as the one passed in. This checker
286 // doesn't check if the SC should succeed or fail, it just checks the
287 // value.
288 if (unverifiedReq && res && unverifiedReq->extraDataValid())
289 *res = unverifiedReq->getExtraData();

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299 unverifiedReq->getExtraData() : true;
300 }
301
302 // If the request is to ZERO a cache block, there is no data to check
303 // against, but it's all zero. We need something to compare to, so use a
304 // const set of zeros.
305 if (flags & Request::STORE_NO_DATA) {
306 assert(!data);
307 assert(sizeof(zero_data) <= fullSize);
308 data = zero_data;
309 }
310
311 if (unverifiedReq && unverifiedMemData &&
312 memcmp(data, unverifiedMemData, fullSize) && extraData) {
313 warn("%lli: Store value does not match value sent to memory! "
314 "data: %#x inst_data: %#x", curTick(), data,
315 unverifiedMemData);
316 handleError();
317 }
318
319 return fault;
320}

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