1/*
2 * Copyright (c) 2011,2013,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64{
65 masterId = systemPtr->getMasterId(this);
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70 tc(NULL), thread(NULL)
71{
72 memReq = NULL;
73 curStaticInst = NULL;
74 curMacroStaticInst = NULL;
75
76 numInst = 0;
77 startNumInst = 0;
78 numLoad = 0;
79 startNumLoad = 0;
80 youngestSN = 0;

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151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 memReq = new Request(0, addr, size, flags, masterId,
160 thread->pcState().instAddr(), tc->contextId());
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = Packet::createRead(memReq);
176
177 pkt->dataStatic(data);
178
179 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
180 // Access memory to see if we have the same data
181 dcachePort->sendFunctional(pkt);
182 } else {
183 // Assume the data is correct if it's an uncached access
184 memcpy(data, unverifiedMemData, size);
185 }
186
187 delete memReq;
188 memReq = NULL;
189 delete pkt;
190 }
191
192 if (fault != NoFault) {
193 if (memReq->isPrefetch()) {
194 fault = NoFault;
195 }
196 delete memReq;
197 memReq = NULL;
198 break;
199 }
200
201 if (memReq != NULL) {
202 delete memReq;
203 }
204
205 //If we don't need to access a second cache line, stop now.
206 if (secondAddr <= addr)
207 {
208 break;
209 }
210
211 // Setup for accessing next cache line
212 data += size;

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239
240 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
241
242 if (secondAddr > addr)
243 size = secondAddr - addr;
244
245 // Need to account for a multiple access like Atomic and Timing CPUs
246 while (1) {
247 memReq = new Request(0, addr, size, flags, masterId,
248 thread->pcState().instAddr(), tc->contextId());
249
250 // translate to physical address
251 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
252
253 if (!checked_flags && fault == NoFault && unverifiedReq) {
254 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
255 memReq->getPaddr(), memReq->getFlags());
256 pAddr = memReq->getPaddr();
257 checked_flags = true;
258 }
259
260 /*
261 * We don't actually check memory for the store because there
262 * is no guarantee it has left the lsq yet, and therefore we
263 * can't verify the memory on stores without lsq snooping
264 * enabled. This is left as future work for the Checker: LSQ snooping
265 * and memory validation after stores have committed.
266 */
267 bool was_prefetch = memReq->isPrefetch();
268
269 delete memReq;
270
271 //If we don't need to access a second cache line, stop now.
272 if (fault != NoFault || secondAddr <= addr)
273 {
274 if (fault != NoFault && was_prefetch) {
275 fault = NoFault;
276 }
277 break;
278 }

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332{
333 return vtophys(tc, addr);
334}
335
336/**
337 * Checks if the flags set by the Checker and Checkee match.
338 */
339bool
340CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
341 Addr pAddr, int flags)
342{
343 Addr unverifiedVAddr = unverified_req->getVaddr();
344 Addr unverifiedPAddr = unverified_req->getPaddr();
345 int unverifiedFlags = unverified_req->getFlags();
346
347 if (unverifiedVAddr != vAddr ||
348 unverifiedPAddr != pAddr ||

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