1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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124
125void
126CheckerCPU::setDcachePort(MasterPort *dcache_port)
127{
128 dcachePort = dcache_port;
129}
130
131void
132CheckerCPU::serialize(ostream &os)
133{
134}
135
136void
137CheckerCPU::unserialize(Checkpoint *cp, const string &section)
138{
139}
140
141Fault
142CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
143{
144 Fault fault = NoFault;
145 int fullSize = size;

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