1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Geoffrey Blake
42 */
43
44#include <list>
45#include <string>
46
47#include "cpu/checker/cpu.hh"
48#include "cpu/base.hh"
49#include "cpu/simple_thread.hh"
50#include "cpu/static_inst.hh"
51#include "cpu/thread_context.hh"
52#include "params/CheckerCPU.hh"
53#include "sim/tlb.hh"
54
55#if FULL_SYSTEM
56#include "arch/kernel_stats.hh"
57#include "arch/vtophys.hh"
58#endif // FULL_SYSTEM
59
60using namespace std;
61using namespace TheISA;
62
63void
64CheckerCPU::init()
65{
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69 : BaseCPU(p), thread(NULL), tc(NULL)
70{
71 memReq = NULL;
72 curStaticInst = NULL;
73 curMacroStaticInst = NULL;
74
75 numInst = 0;
76 startNumInst = 0;
77 numLoad = 0;
78 startNumLoad = 0;
79 youngestSN = 0;
80
81 changedPC = willChangePC = changedNextPC = false;
82
83 exitOnError = p->exitOnError;
84 warnOnlyOnLoadError = p->warnOnlyOnLoadError;
85 itb = p->itb;
86 dtb = p->dtb;
87#if FULL_SYSTEM
88 systemPtr = NULL;
89#else
90 workload = p->workload;
91 // XXX: This is a hack to get this to work some
92 thread = new SimpleThread(this, /* thread_num */ 0, workload[0], itb, dtb);
93
94 tc = thread->getTC();
95 threadContexts.push_back(tc);
96#endif
97
98 updateOnError = true;
99}
100
101CheckerCPU::~CheckerCPU()
102{
103}
104
105void
106CheckerCPU::setSystem(System *system)

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127CheckerCPU::setDcachePort(Port *dcache_port)
128{
129 dcachePort = dcache_port;
130}
131
132void
133CheckerCPU::serialize(ostream &os)
134{
135}
136
137void
138CheckerCPU::unserialize(Checkpoint *cp, const string &section)
139{
140}
141
142Fault
143CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
144{
145 Fault fault = NoFault;
146 unsigned blockSize = dcachePort->peerBlockSize();
147 int fullSize = size;
148 Addr secondAddr = roundDown(addr + size - 1, blockSize);
149 bool checked_flags = false;
150 bool flags_match = true;
151 Addr pAddr = 0x0;
152
153
154 if (secondAddr > addr)
155 size = secondAddr - addr;
156
157 // Need to account for multiple accesses like the Atomic and TimingSimple
158 while (1) {
159 memReq = new Request();
160 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
161
162 // translate to physical address
163 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
164
165 if (!checked_flags && fault == NoFault && unverifiedReq) {
166 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
167 memReq->getPaddr(), memReq->getFlags());
168 pAddr = memReq->getPaddr();
169 checked_flags = true;
170 }
171
172 // Now do the access
173 if (fault == NoFault &&
174 !memReq->getFlags().isSet(Request::NO_ACCESS)) {
175 PacketPtr pkt = new Packet(memReq,
176 memReq->isLLSC() ?
177 MemCmd::LoadLockedReq : MemCmd::ReadReq,
178 Packet::Broadcast);
179
180 pkt->dataStatic(data);
181
182 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
183 // Access memory to see if we have the same data
184 dcachePort->sendFunctional(pkt);
185 } else {
186 // Assume the data is correct if it's an uncached access
187 memcpy(data, unverifiedMemData, size);
188 }
189
190 delete memReq;
191 memReq = NULL;
192 delete pkt;
193 }
194
195 if (fault != NoFault) {
196 if (memReq->isPrefetch()) {
197 fault = NoFault;
198 }
199 delete memReq;
200 memReq = NULL;
201 break;
202 }
203
204 if (memReq != NULL) {
205 delete memReq;
206 }
207
208 //If we don't need to access a second cache line, stop now.
209 if (secondAddr <= addr)
210 {
211 break;
212 }
213
214 // Setup for accessing next cache line
215 data += size;
216 unverifiedMemData += size;
217 size = addr + fullSize - secondAddr;
218 addr = secondAddr;
219 }
220
221 if (!flags_match) {
222 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
223 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
224 unverifiedReq->getFlags(), addr, pAddr, flags);
225 handleError();
226 }
227
228 return fault;
229}
230
231Fault
232CheckerCPU::writeMem(uint8_t *data, unsigned size,
233 Addr addr, unsigned flags, uint64_t *res)
234{
235 Fault fault = NoFault;
236 bool checked_flags = false;
237 bool flags_match = true;
238 Addr pAddr = 0x0;
239
240 unsigned blockSize = dcachePort->peerBlockSize();
241 int fullSize = size;
242
243 Addr secondAddr = roundDown(addr + size - 1, blockSize);
244
245 if (secondAddr > addr)
246 size = secondAddr - addr;
247
248 // Need to account for a multiple access like Atomic and Timing CPUs
249 while (1) {
250 memReq = new Request();
251 memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
252
253 // translate to physical address
254 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
255
256 if (!checked_flags && fault == NoFault && unverifiedReq) {
257 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
258 memReq->getPaddr(), memReq->getFlags());
259 pAddr = memReq->getPaddr();
260 checked_flags = true;
261 }
262
263 /*
264 * We don't actually check memory for the store because there
265 * is no guarantee it has left the lsq yet, and therefore we
266 * can't verify the memory on stores without lsq snooping
267 * enabled. This is left as future work for the Checker: LSQ snooping
268 * and memory validation after stores have committed.
269 */
270
271 delete memReq;
272
273 //If we don't need to access a second cache line, stop now.
274 if (fault != NoFault || secondAddr <= addr)
275 {
276 if (fault != NoFault && memReq->isPrefetch()) {
277 fault = NoFault;
278 }
279 break;
280 }
281
282 //Update size and access address
283 size = addr + fullSize - secondAddr;
284 //And access the right address.
285 addr = secondAddr;
286 }
287
288 if (!flags_match) {
289 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
290 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
291 unverifiedReq->getFlags(), addr, pAddr, flags);
292 handleError();
293 }
294
295 // Assume the result was the same as the one passed in. This checker
296 // doesn't check if the SC should succeed or fail, it just checks the
297 // value.
298 if (unverifiedReq && res && unverifiedReq->extraDataValid())
299 *res = unverifiedReq->getExtraData();
300
301 // Entire purpose here is to make sure we are getting the
302 // same data to send to the mem system as the CPU did.
303 // Cannot check this is actually what went to memory because
304 // there stores can be in ld/st queue or coherent operations
305 // overwriting values.
306 bool extraData;
307 if (unverifiedReq) {
308 extraData = unverifiedReq->extraDataValid() ?
309 unverifiedReq->getExtraData() : 1;
310 }
311
312 if (unverifiedReq && unverifiedMemData &&
313 memcmp(data, unverifiedMemData, fullSize) && extraData) {
314 warn("%lli: Store value does not match value sent to memory!\
315 data: %#x inst_data: %#x", curTick(), data,
316 unverifiedMemData);
317 handleError();
318 }
319
320 return fault;
321}
322
323#if FULL_SYSTEM
324Addr
325CheckerCPU::dbg_vtophys(Addr addr)
326{
327 return vtophys(tc, addr);
328}
329#endif // FULL_SYSTEM
330
331/**
332 * Checks if the flags set by the Checker and Checkee match.
333 */
334bool
335CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
336 Addr pAddr, int flags)
337{
338 Addr unverifiedVAddr = unverified_req->getVaddr();
339 Addr unverifiedPAddr = unverified_req->getPaddr();
340 int unverifiedFlags = unverified_req->getFlags();
341
342 if (unverifiedVAddr != vAddr ||
343 unverifiedPAddr != pAddr ||
344 unverifiedFlags != flags) {
345 return false;
346 }
347
348 return true;
349}
350
351void
352CheckerCPU::dumpAndExit()
353{
354 warn("%lli: Checker PC:%s",
355 curTick(), thread->pcState());
356 panic("Checker found an error!");
357}