base_dyn_inst.hh (9920:028e4da64b42) base_dyn_inst.hh (9932:2efeed2cef09)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1004
1005 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1006 WholeTranslationState *state =
1007 new WholeTranslationState(req, NULL, res, mode);
1008
1009 // One translation if the request isn't split.
1010 DataTranslation<BaseDynInstPtr> *trans =
1011 new DataTranslation<BaseDynInstPtr>(this, state);
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 995 unchanged lines hidden (view full) ---

1004
1005 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1006 WholeTranslationState *state =
1007 new WholeTranslationState(req, NULL, res, mode);
1008
1009 // One translation if the request isn't split.
1010 DataTranslation<BaseDynInstPtr> *trans =
1011 new DataTranslation<BaseDynInstPtr>(this, state);
1012
1012 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1013 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1014
1013 if (!translationCompleted()) {
1015 if (!translationCompleted()) {
1016 // The translation isn't yet complete, so we can't possibly have a
1017 // fault. Overwrite any existing fault we might have from a previous
1018 // execution of this instruction (e.g. an uncachable load that
1019 // couldn't execute because it wasn't at the head of the ROB).
1020 fault = NoFault;
1021
1014 // Save memory requests.
1015 savedReq = state->mainReq;
1016 savedSreqLow = state->sreqLow;
1017 savedSreqHigh = state->sreqHigh;
1018 }
1019 } else {
1020 WholeTranslationState *state =
1021 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1022
1023 // Two translations when the request is split.
1024 DataTranslation<BaseDynInstPtr> *stransLow =
1025 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1026 DataTranslation<BaseDynInstPtr> *stransHigh =
1027 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1028
1029 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1030 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1022 // Save memory requests.
1023 savedReq = state->mainReq;
1024 savedSreqLow = state->sreqLow;
1025 savedSreqHigh = state->sreqHigh;
1026 }
1027 } else {
1028 WholeTranslationState *state =
1029 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1030
1031 // Two translations when the request is split.
1032 DataTranslation<BaseDynInstPtr> *stransLow =
1033 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1034 DataTranslation<BaseDynInstPtr> *stransHigh =
1035 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1036
1037 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1038 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1039
1031 if (!translationCompleted()) {
1040 if (!translationCompleted()) {
1041 // The translation isn't yet complete, so we can't possibly have a
1042 // fault. Overwrite any existing fault we might have from a previous
1043 // execution of this instruction (e.g. an uncachable load that
1044 // couldn't execute because it wasn't at the head of the ROB).
1045 fault = NoFault;
1046
1032 // Save memory requests.
1033 savedReq = state->mainReq;
1034 savedSreqLow = state->sreqLow;
1035 savedSreqHigh = state->sreqHigh;
1036 }
1037 }
1038}
1039

--- 26 unchanged lines hidden --- 		1047 // Save memory requests.
1048 savedReq = state->mainReq;
1049 savedSreqLow = state->sreqLow;
1050 savedSreqHigh = state->sreqHigh;
1051 }
1052 }
1053}
1054

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