base_dyn_inst.hh (8850:ed91b534ed04) base_dyn_inst.hh (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "config/use_checker.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"

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172 /**
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
175 */
176 RequestPtr savedReq;
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
179
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"

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172 /**
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
175 */
176 RequestPtr savedReq;
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
179
180#if USE_CHECKER
181 // Need a copy of main request pointer to verify on writes.
182 RequestPtr reqToVerify;
180 // Need a copy of main request pointer to verify on writes.
181 RequestPtr reqToVerify;
183#endif //USE_CHECKER
184
185 /** @todo: Consider making this private. */
186 public:
187 /** The sequence number of the instruction. */
188 InstSeqNum seqNum;
189
190 enum Status {
191 IqEntry, /// Instruction is in the IQ

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891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
892 }
893
894 if (translationCompleted) {
895 if (fault == NoFault) {
896 effAddr = req->getVaddr();
897 effSize = size;
898 effAddrValid = true;
182
183 /** @todo: Consider making this private. */
184 public:
185 /** The sequence number of the instruction. */
186 InstSeqNum seqNum;
187
188 enum Status {
189 IqEntry, /// Instruction is in the IQ

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889 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
890 }
891
892 if (translationCompleted) {
893 if (fault == NoFault) {
894 effAddr = req->getVaddr();
895 effSize = size;
896 effAddrValid = true;
899#if USE_CHECKER
900 if (reqToVerify != NULL) {
901 delete reqToVerify;
897
898 if (cpu->checker) {
899 if (reqToVerify != NULL) {
900 delete reqToVerify;
901 }
902 reqToVerify = new Request(*req);
902 }
903 }
903 reqToVerify = new Request(*req);
904#endif //USE_CHECKER
905 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
906 } else {
907 // Commit will have to clean up whatever happened. Set this
908 // instruction as executed.
909 this->setExecuted();
910 }
911
912 if (fault != NoFault) {

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952 }
953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
954 }
955
956 if (fault == NoFault && translationCompleted) {
957 effAddr = req->getVaddr();
958 effSize = size;
959 effAddrValid = true;
904 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
905 } else {
906 // Commit will have to clean up whatever happened. Set this
907 // instruction as executed.
908 this->setExecuted();
909 }
910
911 if (fault != NoFault) {

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951 }
952 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
953 }
954
955 if (fault == NoFault && translationCompleted) {
956 effAddr = req->getVaddr();
957 effSize = size;
958 effAddrValid = true;
960#if USE_CHECKER
961 if (reqToVerify != NULL) {
962 delete reqToVerify;
959
960 if (cpu->checker) {
961 if (reqToVerify != NULL) {
962 delete reqToVerify;
963 }
964 reqToVerify = new Request(*req);
963 }
965 }
964 reqToVerify = new Request(*req);
965#endif // USE_CHECKER
966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>
973inline void

--- 85 unchanged lines hidden --- 		966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>
973inline void

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