base_dyn_inst.hh (8817:c36441eed919) base_dyn_inst.hh (8832:247fee427324)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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419 void dump();
420
421 /** Dumps out contents of this BaseDynInst into given string. */
422 void dump(std::string &outstring);
423
424 /** Read this CPU's ID. */
425 int cpuId() { return cpu->cpuId(); }
426
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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419 void dump();
420
421 /** Dumps out contents of this BaseDynInst into given string. */
422 void dump(std::string &outstring);
423
424 /** Read this CPU's ID. */
425 int cpuId() { return cpu->cpuId(); }
426
427 /** Read this CPU's data requestor ID */
428 MasterID masterId() { return cpu->dataMasterId(); }
429
427 /** Read this context's system-wide ID **/
428 int contextId() { return thread->contextId(); }
429
430 /** Returns the fault type. */
431 Fault getFault() { return fault; }
432
433 /** Checks whether or not this instruction has had its branch target
434 * calculated yet. For now it is not utilized and is hacked to be

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873 Request *sreqLow = NULL;
874 Request *sreqHigh = NULL;
875
876 if (reqMade && translationStarted) {
877 req = savedReq;
878 sreqLow = savedSreqLow;
879 sreqHigh = savedSreqHigh;
880 } else {
430 /** Read this context's system-wide ID **/
431 int contextId() { return thread->contextId(); }
432
433 /** Returns the fault type. */
434 Fault getFault() { return fault; }
435
436 /** Checks whether or not this instruction has had its branch target
437 * calculated yet. For now it is not utilized and is hacked to be

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876 Request *sreqLow = NULL;
877 Request *sreqHigh = NULL;
878
879 if (reqMade && translationStarted) {
880 req = savedReq;
881 sreqLow = savedSreqLow;
882 sreqHigh = savedSreqHigh;
883 } else {
881 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
884 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
882 thread->contextId(), threadNumber);
883
884 // Only split the request if the ISA supports unaligned accesses.
885 if (TheISA::HasUnalignedMemAcc) {
886 splitRequest(req, sreqLow, sreqHigh);
887 }
888 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
889 }

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935 Request *sreqLow = NULL;
936 Request *sreqHigh = NULL;
937
938 if (reqMade && translationStarted) {
939 req = savedReq;
940 sreqLow = savedSreqLow;
941 sreqHigh = savedSreqHigh;
942 } else {
885 thread->contextId(), threadNumber);
886
887 // Only split the request if the ISA supports unaligned accesses.
888 if (TheISA::HasUnalignedMemAcc) {
889 splitRequest(req, sreqLow, sreqHigh);
890 }
891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
892 }

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938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (reqMade && translationStarted) {
942 req = savedReq;
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
945 } else {
943 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
944 thread->contextId(), threadNumber);
945
946 // Only split the request if the ISA supports unaligned accesses.
947 if (TheISA::HasUnalignedMemAcc) {
948 splitRequest(req, sreqLow, sreqHigh);
949 }
950 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
951 }

--- 104 unchanged lines hidden --- 		947 thread->contextId(), threadNumber);
948
949 // Only split the request if the ISA supports unaligned accesses.
950 if (TheISA::HasUnalignedMemAcc) {
951 splitRequest(req, sreqLow, sreqHigh);
952 }
953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
954 }

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