base_dyn_inst.hh (8443:530ff1bc8d70) base_dyn_inst.hh (8444:56de1f9320df)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128
128
129 Fault writeBytes(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,

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836
837 /** Sets the number of consecutive store conditional failures. */
838 void setStCondFailures(unsigned sc_failures)
839 { thread->storeCondFailures = sc_failures; }
840};
841
842template<class Impl>
843Fault
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,

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836
837 /** Sets the number of consecutive store conditional failures. */
838 void setStCondFailures(unsigned sc_failures)
839 { thread->storeCondFailures = sc_failures; }
840};
841
842template<class Impl>
843Fault
844BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
845 unsigned size, unsigned flags)
844BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
845 unsigned size, unsigned flags)
846{
847 reqMade = true;
848 Request *req = NULL;
849 Request *sreqLow = NULL;
850 Request *sreqHigh = NULL;
851
852 if (reqMade && translationStarted) {
853 req = savedReq;

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888 traceData->setAddr(addr);
889 }
890
891 return fault;
892}
893
894template<class Impl>
895Fault
846{
847 reqMade = true;
848 Request *req = NULL;
849 Request *sreqLow = NULL;
850 Request *sreqHigh = NULL;
851
852 if (reqMade && translationStarted) {
853 req = savedReq;

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888 traceData->setAddr(addr);
889 }
890
891 return fault;
892}
893
894template<class Impl>
895Fault
896BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
897 Addr addr, unsigned flags, uint64_t *res)
896BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
897 Addr addr, unsigned flags, uint64_t *res)
898{
899 if (traceData) {
900 traceData->setAddr(addr);
901 }
902
903 reqMade = true;
904 Request *req = NULL;
905 Request *sreqLow = NULL;

--- 114 unchanged lines hidden --- 		898{
899 if (traceData) {
900 traceData->setAddr(addr);
901 }
902
903 reqMade = true;
904 Request *req = NULL;
905 Request *sreqLow = NULL;

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