base_dyn_inst.hh (8201:89221928d131) base_dyn_inst.hh (8443:530ff1bc8d70)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 /**
128 * Does a read to a given address.
129 * @param addr The address to read.
130 * @param data The read's data is written into this parameter.
131 * @param flags The request's flags.
132 * @return Returns any fault due to the read.
133 */
134 template <class T>
135 Fault read(Addr addr, T &data, unsigned flags);
136
137 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
138
127 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128
139 /**
140 * Does a write to a given address.
141 * @param data The data to be written.
142 * @param addr The address to write to.
143 * @param flags The request's flags.
144 * @param res The result of the write (for load locked/store conditionals).
145 * @return Returns any fault due to the write.
146 */
147 template <class T>
148 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
149
150 Fault writeBytes(uint8_t *data, unsigned size,
151 Addr addr, unsigned flags, uint64_t *res);
152
153 /** Splits a request in two if it crosses a dcache block. */
154 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
155 RequestPtr &sreqHigh);
156
157 /** Initiate a DTB address translation. */

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908 if (traceData) {
909 traceData->setAddr(addr);
910 }
911
912 return fault;
913}
914
915template<class Impl>
129 Fault writeBytes(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */

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887 if (traceData) {
888 traceData->setAddr(addr);
889 }
890
891 return fault;
892}
893
894template<class Impl>
916template<class T>
917inline Fault
918BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
919{
920 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
921
922 data = TheISA::gtoh(data);
923
924 if (traceData) {
925 traceData->setData(data);
926 }
927
928 return fault;
929}
930
931template<class Impl>
932Fault
933BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
934 Addr addr, unsigned flags, uint64_t *res)
935{
936 if (traceData) {
937 traceData->setAddr(addr);
938 }
939

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963 effAddrValid = true;
964 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
965 }
966
967 return fault;
968}
969
970template<class Impl>
895Fault
896BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
897 Addr addr, unsigned flags, uint64_t *res)
898{
899 if (traceData) {
900 traceData->setAddr(addr);
901 }
902

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926 effAddrValid = true;
927 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
928 }
929
930 return fault;
931}
932
933template<class Impl>
971template<class T>
972inline Fault
973BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
974{
975 if (traceData) {
976 traceData->setData(data);
977 }
978 data = TheISA::htog(data);
979 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
980}
981
982template<class Impl>
983inline void
984BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
985 RequestPtr &sreqHigh)
986{
987 // Check to see if the request crosses the next level block boundary.
988 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
989 Addr addr = req->getVaddr();
990 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);

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935BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
936 RequestPtr &sreqHigh)
937{
938 // Check to see if the request crosses the next level block boundary.
939 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
940 Addr addr = req->getVaddr();
941 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);

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