base_dyn_inst.hh (7944:1daf51f62013) base_dyn_inst.hh (8199:3d6c08c877a9)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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238 Fault fault;
239
240 /** Pointer to the data for the memory access. */
241 uint8_t *memData;
242
243 /** The effective virtual address (lds & stores only). */
244 Addr effAddr;
245
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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238 Fault fault;
239
240 /** Pointer to the data for the memory access. */
241 uint8_t *memData;
242
243 /** The effective virtual address (lds & stores only). */
244 Addr effAddr;
245
246 /** The size of the request */
247 Addr effSize;
248
246 /** Is the effective virtual address valid. */
247 bool effAddrValid;
248
249 /** The effective physical address. */
250 Addr physEffAddr;
251
252 /** Effective virtual address for a copy source. */
253 Addr copySrcEffAddr;

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887 splitRequest(req, sreqLow, sreqHigh);
888 }
889 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
890 }
891
892 if (translationCompleted) {
893 if (fault == NoFault) {
894 effAddr = req->getVaddr();
249 /** Is the effective virtual address valid. */
250 bool effAddrValid;
251
252 /** The effective physical address. */
253 Addr physEffAddr;
254
255 /** Effective virtual address for a copy source. */
256 Addr copySrcEffAddr;

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890 splitRequest(req, sreqLow, sreqHigh);
891 }
892 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
893 }
894
895 if (translationCompleted) {
896 if (fault == NoFault) {
897 effAddr = req->getVaddr();
898 effSize = size;
895 effAddrValid = true;
896 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
897 } else {
898 // Commit will have to clean up whatever happened. Set this
899 // instruction as executed.
900 this->setExecuted();
901 }
902

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957 if (TheISA::HasUnalignedMemAcc) {
958 splitRequest(req, sreqLow, sreqHigh);
959 }
960 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
961 }
962
963 if (fault == NoFault && translationCompleted) {
964 effAddr = req->getVaddr();
899 effAddrValid = true;
900 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
901 } else {
902 // Commit will have to clean up whatever happened. Set this
903 // instruction as executed.
904 this->setExecuted();
905 }
906

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961 if (TheISA::HasUnalignedMemAcc) {
962 splitRequest(req, sreqLow, sreqHigh);
963 }
964 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
965 }
966
967 if (fault == NoFault && translationCompleted) {
968 effAddr = req->getVaddr();
969 effSize = size;
965 effAddrValid = true;
966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>

--- 98 unchanged lines hidden --- 		970 effAddrValid = true;
971 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
972 }
973
974 return fault;
975}
976
977template<class Impl>

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