base_dyn_inst.hh (7678:f19b6a3a8cec) | base_dyn_inst.hh (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 24 unchanged lines hidden (view full) --- 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 24 unchanged lines hidden (view full) --- 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" |
41#include "arch/utility.hh" |
|
41#include "base/fast_alloc.hh" 42#include "base/trace.hh" 43#include "config/full_system.hh" 44#include "config/the_isa.hh" 45#include "cpu/o3/comm.hh" 46#include "cpu/exetrace.hh" 47#include "cpu/inst_seq.hh" 48#include "cpu/op_class.hh" --- 187 unchanged lines hidden (view full) --- 236 /** The result of the instruction; assumes for now that there's only one 237 * destination register. 238 */ 239 Result instResult; 240 241 /** Records changes to result? */ 242 bool recordResult; 243 | 42#include "base/fast_alloc.hh" 43#include "base/trace.hh" 44#include "config/full_system.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/comm.hh" 47#include "cpu/exetrace.hh" 48#include "cpu/inst_seq.hh" 49#include "cpu/op_class.hh" --- 187 unchanged lines hidden (view full) --- 237 /** The result of the instruction; assumes for now that there's only one 238 * destination register. 239 */ 240 Result instResult; 241 242 /** Records changes to result? */ 243 bool recordResult; 244 |
244 /** PC of this instruction. */ 245 Addr PC; 246 247 /** Micro PC of this instruction. */ 248 Addr microPC; 249 | |
250 /** Did this instruction execute, or is it predicated false */ 251 bool predicate; 252 253 protected: | 245 /** Did this instruction execute, or is it predicated false */ 246 bool predicate; 247 248 protected: |
254 /** Next non-speculative PC. It is not filled in at fetch, but rather 255 * once the target of the branch is truly known (either decode or 256 * execute). 257 */ 258 Addr nextPC; | 249 /** PC state for this instruction. */ 250 TheISA::PCState pc; |
259 | 251 |
260 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 261 Addr nextNPC; | 252 /** Predicted PC state after this instruction. */ 253 TheISA::PCState predPC; |
262 | 254 |
263 /** Next non-speculative micro PC. */ 264 Addr nextMicroPC; 265 266 /** Predicted next PC. */ 267 Addr predPC; 268 269 /** Predicted next NPC. */ 270 Addr predNPC; 271 272 /** Predicted next microPC */ 273 Addr predMicroPC; 274 | |
275 /** If this is a branch that was predicted taken */ 276 bool predTaken; 277 278 public: 279 280#ifdef DEBUG 281 void dumpSNList(); 282#endif --- 98 unchanged lines hidden (view full) --- 381 * index. 382 */ 383 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 384 { 385 _flatDestRegIdx[idx] = flattened_dest; 386 } 387 /** BaseDynInst constructor given a binary instruction. 388 * @param staticInst A StaticInstPtr to the underlying instruction. | 255 /** If this is a branch that was predicted taken */ 256 bool predTaken; 257 258 public: 259 260#ifdef DEBUG 261 void dumpSNList(); 262#endif --- 98 unchanged lines hidden (view full) --- 361 * index. 362 */ 363 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 364 { 365 _flatDestRegIdx[idx] = flattened_dest; 366 } 367 /** BaseDynInst constructor given a binary instruction. 368 * @param staticInst A StaticInstPtr to the underlying instruction. |
389 * @param PC The PC of the instruction. 390 * @param pred_PC The predicted next PC. 391 * @param pred_NPC The predicted next NPC. | 369 * @param pc The PC state for the instruction. 370 * @param predPC The predicted next PC state for the instruction. |
392 * @param seq_num The sequence number of the instruction. 393 * @param cpu Pointer to the instruction's CPU. 394 */ | 371 * @param seq_num The sequence number of the instruction. 372 * @param cpu Pointer to the instruction's CPU. 373 */ |
395 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 396 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 397 InstSeqNum seq_num, ImplCPU *cpu); | 374 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 375 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); |
398 399 /** BaseDynInst constructor given a binary instruction. 400 * @param inst The binary instruction. | 376 377 /** BaseDynInst constructor given a binary instruction. 378 * @param inst The binary instruction. |
401 * @param PC The PC of the instruction. 402 * @param pred_PC The predicted next PC. 403 * @param pred_NPC The predicted next NPC. | 379 * @param _pc The PC state for the instruction. 380 * @param _predPC The predicted next PC state for the instruction. |
404 * @param seq_num The sequence number of the instruction. 405 * @param cpu Pointer to the instruction's CPU. 406 */ | 381 * @param seq_num The sequence number of the instruction. 382 * @param cpu Pointer to the instruction's CPU. 383 */ |
407 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 408 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 409 InstSeqNum seq_num, ImplCPU *cpu); | 384 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 385 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); |
410 411 /** BaseDynInst constructor given a StaticInst pointer. 412 * @param _staticInst The StaticInst for this BaseDynInst. 413 */ 414 BaseDynInst(StaticInstPtr &_staticInst); 415 416 /** BaseDynInst destructor. */ 417 ~BaseDynInst(); --- 20 unchanged lines hidden (view full) --- 438 439 /** Checks whether or not this instruction has had its branch target 440 * calculated yet. For now it is not utilized and is hacked to be 441 * always false. 442 * @todo: Actually use this instruction. 443 */ 444 bool doneTargCalc() { return false; } 445 | 386 387 /** BaseDynInst constructor given a StaticInst pointer. 388 * @param _staticInst The StaticInst for this BaseDynInst. 389 */ 390 BaseDynInst(StaticInstPtr &_staticInst); 391 392 /** BaseDynInst destructor. */ 393 ~BaseDynInst(); --- 20 unchanged lines hidden (view full) --- 414 415 /** Checks whether or not this instruction has had its branch target 416 * calculated yet. For now it is not utilized and is hacked to be 417 * always false. 418 * @todo: Actually use this instruction. 419 */ 420 bool doneTargCalc() { return false; } 421 |
446 /** Returns the next PC. This could be the speculative next PC if it is 447 * called prior to the actual branch target being calculated. 448 */ 449 Addr readNextPC() { return nextPC; } 450 451 /** Returns the next NPC. This could be the speculative next NPC if it is 452 * called prior to the actual branch target being calculated. 453 */ 454 Addr readNextNPC() 455 { 456#if ISA_HAS_DELAY_SLOT 457 return nextNPC; 458#else 459 return nextPC + sizeof(TheISA::MachInst); 460#endif 461 } 462 463 Addr readNextMicroPC() 464 { 465 return nextMicroPC; 466 } 467 | |
468 /** Set the predicted target of this current instruction. */ | 422 /** Set the predicted target of this current instruction. */ |
469 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 470 Addr predicted_MicroPC) | 423 void setPredTarg(const TheISA::PCState &_predPC) |
471 { | 424 { |
472 predPC = predicted_PC; 473 predNPC = predicted_NPC; 474 predMicroPC = predicted_MicroPC; | 425 predPC = _predPC; |
475 } 476 | 426 } 427 |
428 const TheISA::PCState &readPredTarg() { return predPC; } 429 |
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477 /** Returns the predicted PC immediately after the branch. */ | 430 /** Returns the predicted PC immediately after the branch. */ |
478 Addr readPredPC() { return predPC; } | 431 Addr predInstAddr() { return predPC.instAddr(); } |
479 480 /** Returns the predicted PC two instructions after the branch */ | 432 433 /** Returns the predicted PC two instructions after the branch */ |
481 Addr readPredNPC() { return predNPC; } | 434 Addr predNextInstAddr() { return predPC.nextInstAddr(); } |
482 483 /** Returns the predicted micro PC after the branch */ | 435 436 /** Returns the predicted micro PC after the branch */ |
484 Addr readPredMicroPC() { return predMicroPC; } | 437 Addr predMicroPC() { return predPC.microPC(); } |
485 486 /** Returns whether the instruction was predicted taken or not. */ 487 bool readPredTaken() 488 { 489 return predTaken; 490 } 491 492 void setPredTaken(bool predicted_taken) 493 { 494 predTaken = predicted_taken; 495 } 496 497 /** Returns whether the instruction mispredicted. */ 498 bool mispredicted() 499 { | 438 439 /** Returns whether the instruction was predicted taken or not. */ 440 bool readPredTaken() 441 { 442 return predTaken; 443 } 444 445 void setPredTaken(bool predicted_taken) 446 { 447 predTaken = predicted_taken; 448 } 449 450 /** Returns whether the instruction mispredicted. */ 451 bool mispredicted() 452 { |
500 return readPredPC() != readNextPC() || 501 readPredNPC() != readNextNPC() || 502 readPredMicroPC() != readNextMicroPC(); | 453 TheISA::PCState tempPC = pc; 454 TheISA::advancePC(tempPC, staticInst); 455 return !(tempPC == predPC); |
503 } 504 505 // 506 // Instruction types. Forward checks to StaticInst object. 507 // 508 bool isNop() const { return staticInst->isNop(); } 509 bool isMemRef() const { return staticInst->isMemRef(); } 510 bool isLoad() const { return staticInst->isLoad(); } --- 60 unchanged lines hidden (view full) --- 571 * serializing state. 572 */ 573 bool isSerializeHandled() { return status[SerializeHandled]; } 574 575 /** Returns the opclass of this instruction. */ 576 OpClass opClass() const { return staticInst->opClass(); } 577 578 /** Returns the branch target address. */ | 456 } 457 458 // 459 // Instruction types. Forward checks to StaticInst object. 460 // 461 bool isNop() const { return staticInst->isNop(); } 462 bool isMemRef() const { return staticInst->isMemRef(); } 463 bool isLoad() const { return staticInst->isLoad(); } --- 60 unchanged lines hidden (view full) --- 524 * serializing state. 525 */ 526 bool isSerializeHandled() { return status[SerializeHandled]; } 527 528 /** Returns the opclass of this instruction. */ 529 OpClass opClass() const { return staticInst->opClass(); } 530 531 /** Returns the branch target address. */ |
579 Addr branchTarget() const { return staticInst->branchTarget(PC); } | 532 TheISA::PCState branchTarget() const 533 { return staticInst->branchTarget(pc); } |
580 581 /** Returns the number of source registers. */ 582 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 583 584 /** Returns the number of destination registers. */ 585 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 586 587 // the following are used to track physical register usage --- 180 unchanged lines hidden (view full) --- 768 bool isInROB() const { return status[RobEntry]; } 769 770 /** Sets this instruction as squashed in the ROB. */ 771 void setSquashedInROB() { status.set(SquashedInROB); } 772 773 /** Returns whether or not this instruction is squashed in the ROB. */ 774 bool isSquashedInROB() const { return status[SquashedInROB]; } 775 | 534 535 /** Returns the number of source registers. */ 536 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 537 538 /** Returns the number of destination registers. */ 539 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 540 541 // the following are used to track physical register usage --- 180 unchanged lines hidden (view full) --- 722 bool isInROB() const { return status[RobEntry]; } 723 724 /** Sets this instruction as squashed in the ROB. */ 725 void setSquashedInROB() { status.set(SquashedInROB); } 726 727 /** Returns whether or not this instruction is squashed in the ROB. */ 728 bool isSquashedInROB() const { return status[SquashedInROB]; } 729 |
776 /** Read the PC of this instruction. */ 777 const Addr readPC() const { return PC; } | 730 /** Read the PC state of this instruction. */ 731 const TheISA::PCState pcState() const { return pc; } |
778 | 732 |
779 /**Read the micro PC of this instruction. */ 780 const Addr readMicroPC() const { return microPC; } | 733 /** Set the PC state of this instruction. */ 734 const void pcState(const TheISA::PCState &val) { pc = val; } |
781 | 735 |
782 /** Set the next PC of this instruction (its actual target). */ 783 void setNextPC(Addr val) 784 { 785 nextPC = val; 786 } | 736 /** Read the PC of this instruction. */ 737 const Addr instAddr() const { return pc.instAddr(); } |
787 | 738 |
788 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 789 void setNextNPC(Addr val) 790 { 791#if ISA_HAS_DELAY_SLOT 792 nextNPC = val; 793#endif 794 } | 739 /** Read the PC of the next instruction. */ 740 const Addr nextInstAddr() const { return pc.nextInstAddr(); } |
795 | 741 |
796 void setNextMicroPC(Addr val) 797 { 798 nextMicroPC = val; 799 } | 742 /**Read the micro PC of this instruction. */ 743 const Addr microPC() const { return pc.microPC(); } |
800 801 bool readPredicate() 802 { 803 return predicate; 804 } 805 806 void setPredicate(bool val) 807 { --- 82 unchanged lines hidden (view full) --- 890}; 891 892template<class Impl> 893Fault 894BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 895 unsigned size, unsigned flags) 896{ 897 reqMade = true; | 744 745 bool readPredicate() 746 { 747 return predicate; 748 } 749 750 void setPredicate(bool val) 751 { --- 82 unchanged lines hidden (view full) --- 834}; 835 836template<class Impl> 837Fault 838BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 839 unsigned size, unsigned flags) 840{ 841 reqMade = true; |
898 Request *req = new Request(asid, addr, size, flags, this->PC, | 842 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), |
899 thread->contextId(), threadNumber); 900 901 Request *sreqLow = NULL; 902 Request *sreqHigh = NULL; 903 904 // Only split the request if the ISA supports unaligned accesses. 905 if (TheISA::HasUnalignedMemAcc) { 906 splitRequest(req, sreqLow, sreqHigh); --- 44 unchanged lines hidden (view full) --- 951BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 952 Addr addr, unsigned flags, uint64_t *res) 953{ 954 if (traceData) { 955 traceData->setAddr(addr); 956 } 957 958 reqMade = true; | 843 thread->contextId(), threadNumber); 844 845 Request *sreqLow = NULL; 846 Request *sreqHigh = NULL; 847 848 // Only split the request if the ISA supports unaligned accesses. 849 if (TheISA::HasUnalignedMemAcc) { 850 splitRequest(req, sreqLow, sreqHigh); --- 44 unchanged lines hidden (view full) --- 895BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 896 Addr addr, unsigned flags, uint64_t *res) 897{ 898 if (traceData) { 899 traceData->setAddr(addr); 900 } 901 902 reqMade = true; |
959 Request *req = new Request(asid, addr, size, flags, this->PC, | 903 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), |
960 thread->contextId(), threadNumber); 961 962 Request *sreqLow = NULL; 963 Request *sreqHigh = NULL; 964 965 // Only split the request if the ISA supports unaligned accesses. 966 if (TheISA::HasUnalignedMemAcc) { 967 splitRequest(req, sreqLow, sreqHigh); --- 95 unchanged lines hidden --- | 904 thread->contextId(), threadNumber); 905 906 Request *sreqLow = NULL; 907 Request *sreqHigh = NULL; 908 909 // Only split the request if the ISA supports unaligned accesses. 910 if (TheISA::HasUnalignedMemAcc) { 911 splitRequest(req, sreqLow, sreqHigh); --- 95 unchanged lines hidden --- |