base_dyn_inst.hh (7600:eff7f79f7dfd) base_dyn_inst.hh (7678:f19b6a3a8cec)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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44#include "config/the_isa.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/op_class.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/translation.hh"
51#include "mem/packet.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 35 unchanged lines hidden (view full) ---

44#include "config/the_isa.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/op_class.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/translation.hh"
51#include "mem/packet.hh"
52#include "sim/byteswap.hh"
52#include "sim/system.hh"
53#include "sim/tlb.hh"
54
55/**
56 * @file
57 * Defines a dynamic instruction context.
58 */
59

--- 1002 unchanged lines hidden --- 		53#include "sim/system.hh"
54#include "sim/tlb.hh"
55
56/**
57 * @file
58 * Defines a dynamic instruction context.
59 */
60

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