base_dyn_inst.hh (6974:4d4903a3e7c5) base_dyn_inst.hh (6975:862a31349d43)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 873 unchanged lines hidden (view full) ---

882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
884 }
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
889 effAddrValid = true;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 873 unchanged lines hidden (view full) ---

882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
884 }
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
889 effAddrValid = true;
890 cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
890 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
891 } else {
892
893 // Return a fixed value to keep simulation deterministic even
894 // along misspeculated paths.
895 data = (T)-1;
896
897 // Commit will have to clean up whatever happened. Set this
898 // instruction as executed.

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928 if (TheISA::HasUnalignedMemAcc) {
929 splitRequest(req, sreqLow, sreqHigh);
930 }
931 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
932
933 if (fault == NoFault) {
934 effAddr = req->getVaddr();
935 effAddrValid = true;
891 } else {
892
893 // Return a fixed value to keep simulation deterministic even
894 // along misspeculated paths.
895 data = (T)-1;
896
897 // Commit will have to clean up whatever happened. Set this
898 // instruction as executed.

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928 if (TheISA::HasUnalignedMemAcc) {
929 splitRequest(req, sreqLow, sreqHigh);
930 }
931 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
932
933 if (fault == NoFault) {
934 effAddr = req->getVaddr();
935 effAddrValid = true;
936 cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
936 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
937 }
938
939 return fault;
940}
941
942template<class Impl>
943inline void
944BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,

--- 68 unchanged lines hidden --- 		937 }
938
939 return fault;
940}
941
942template<class Impl>
943inline void
944BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,

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