base_dyn_inst.hh (5737:f43dbc09fad3) base_dyn_inst.hh (5890:bdef71accd68)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 101 unchanged lines hidden (view full) ---

110 * @param addr The address to read.
111 * @param data The read's data is written into this parameter.
112 * @param flags The request's flags.
113 * @return Returns any fault due to the read.
114 */
115 template <class T>
116 Fault read(Addr addr, T &data, unsigned flags);
117
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 101 unchanged lines hidden (view full) ---

110 * @param addr The address to read.
111 * @param data The read's data is written into this parameter.
112 * @param flags The request's flags.
113 * @return Returns any fault due to the read.
114 */
115 template <class T>
116 Fault read(Addr addr, T &data, unsigned flags);
117
118 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
119 int size, unsigned flags);
120
121 /**
122 * Does a write to a given address.
123 * @param data The data to be written.
124 * @param addr The address to write to.
125 * @param flags The request's flags.
126 * @param res The result of the write (for load locked/store conditionals).
127 * @return Returns any fault due to the write.
128 */
129 template <class T>
130 Fault write(T data, Addr addr, unsigned flags,
131 uint64_t *res);
132
118 /**
119 * Does a write to a given address.
120 * @param data The data to be written.
121 * @param addr The address to write to.
122 * @param flags The request's flags.
123 * @param res The result of the write (for load locked/store conditionals).
124 * @return Returns any fault due to the write.
125 */
126 template <class T>
127 Fault write(T data, Addr addr, unsigned flags,
128 uint64_t *res);
129
133 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
134 int size, unsigned flags);
135
136 void prefetch(Addr addr, unsigned flags);
137 void writeHint(Addr addr, int size, unsigned flags);
138 Fault copySrcTranslate(Addr src);
139 Fault copy(Addr dest);
140
141 /** @todo: Consider making this private. */
142 public:
143 /** The sequence number of the instruction. */

--- 708 unchanged lines hidden (view full) ---

852 { return thread->storeCondFailures; }
853
854 /** Sets the number of consecutive store conditional failures. */
855 void setStCondFailures(unsigned sc_failures)
856 { thread->storeCondFailures = sc_failures; }
857};
858
859template<class Impl>
130 void prefetch(Addr addr, unsigned flags);
131 void writeHint(Addr addr, int size, unsigned flags);
132 Fault copySrcTranslate(Addr src);
133 Fault copy(Addr dest);
134
135 /** @todo: Consider making this private. */
136 public:
137 /** The sequence number of the instruction. */

--- 708 unchanged lines hidden (view full) ---

846 { return thread->storeCondFailures; }
847
848 /** Sets the number of consecutive store conditional failures. */
849 void setStCondFailures(unsigned sc_failures)
850 { thread->storeCondFailures = sc_failures; }
851};
852
853template<class Impl>
860Fault
861BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
862 int size, unsigned flags)
863{
864 if (traceData) {
865 traceData->setAddr(vaddr);
866 }
867
868 reqMade = true;
869 Request *req = new Request();
870 req->setVirt(asid, vaddr, size, flags, PC);
871 req->setThreadContext(thread->contextId(), threadNumber);
872
873 fault = cpu->translateDataReadReq(req, thread);
874
875 if (fault == NoFault)
876 paddr = req->getPaddr();
877
878 delete req;
879 return fault;
880}
881
882template<class Impl>
883template<class T>
884inline Fault
885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
886{
887 reqMade = true;
888 Request *req = new Request();
889 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
890 req->setThreadContext(thread->contextId(), threadNumber);
891
854template<class T>
855inline Fault
856BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
857{
858 reqMade = true;
859 Request *req = new Request();
860 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
861 req->setThreadContext(thread->contextId(), threadNumber);
862
892 fault = cpu->translateDataReadReq(req, thread);
863 fault = cpu->dtb->translate(req, thread->getTC(), false);
893
894 if (req->isUncacheable())
895 isUncacheable = true;
896
897 if (fault == NoFault) {
898 effAddr = req->getVaddr();
899 effAddrValid = true;
900 physEffAddr = req->getPaddr();

--- 25 unchanged lines hidden (view full) ---

926 traceData->setAddr(addr);
927 traceData->setData(data);
928 }
929
930 return fault;
931}
932
933template<class Impl>
864
865 if (req->isUncacheable())
866 isUncacheable = true;
867
868 if (fault == NoFault) {
869 effAddr = req->getVaddr();
870 effAddrValid = true;
871 physEffAddr = req->getPaddr();

--- 25 unchanged lines hidden (view full) ---

897 traceData->setAddr(addr);
898 traceData->setData(data);
899 }
900
901 return fault;
902}
903
904template<class Impl>
934Fault
935BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
936 int size, unsigned flags)
937{
938 if (traceData) {
939 traceData->setAddr(vaddr);
940 }
941
942 reqMade = true;
943 Request *req = new Request();
944 req->setVirt(asid, vaddr, size, flags, PC);
945 req->setThreadContext(thread->contextId(), threadNumber);
946
947 fault = cpu->translateDataWriteReq(req, thread);
948
949 if (fault == NoFault)
950 paddr = req->getPaddr();
951
952 delete req;
953 return fault;
954}
955
956template<class Impl>
957template<class T>
958inline Fault
959BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
960{
961 if (traceData) {
962 traceData->setAddr(addr);
963 traceData->setData(data);
964 }
965
966 reqMade = true;
967 Request *req = new Request();
968 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
969 req->setThreadContext(thread->contextId(), threadNumber);
970
905template<class T>
906inline Fault
907BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
908{
909 if (traceData) {
910 traceData->setAddr(addr);
911 traceData->setData(data);
912 }
913
914 reqMade = true;
915 Request *req = new Request();
916 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
917 req->setThreadContext(thread->contextId(), threadNumber);
918
971 fault = cpu->translateDataWriteReq(req, thread);
919 fault = cpu->dtb->translate(req, thread->getTC(), true);
972
973 if (req->isUncacheable())
974 isUncacheable = true;
975
976 if (fault == NoFault) {
977 effAddr = req->getVaddr();
978 effAddrValid = true;
979 physEffAddr = req->getPaddr();

--- 23 unchanged lines hidden --- 		920
921 if (req->isUncacheable())
922 isUncacheable = true;
923
924 if (fault == NoFault) {
925 effAddr = req->getVaddr();
926 effAddrValid = true;
927 physEffAddr = req->getPaddr();

--- 23 unchanged lines hidden ---