base_dyn_inst.hh (5712:199d31b47f7b) | base_dyn_inst.hh (5714:76abee886def) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 400 unchanged lines hidden (view full) --- 409 void dump(); 410 411 /** Dumps out contents of this BaseDynInst into given string. */ 412 void dump(std::string &outstring); 413 414 /** Read this CPU's ID. */ 415 int cpuId() { return cpu->cpuId(); } 416 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 400 unchanged lines hidden (view full) --- 409 void dump(); 410 411 /** Dumps out contents of this BaseDynInst into given string. */ 412 void dump(std::string &outstring); 413 414 /** Read this CPU's ID. */ 415 int cpuId() { return cpu->cpuId(); } 416 |
417 /** Read this context's system-wide ID **/ 418 int contextId() { return thread->contextId(); } 419 |
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417 /** Returns the fault type. */ 418 Fault getFault() { return fault; } 419 420 /** Checks whether or not this instruction has had its branch target 421 * calculated yet. For now it is not utilized and is hacked to be 422 * always false. 423 * @todo: Actually use this instruction. 424 */ --- 438 unchanged lines hidden (view full) --- 863{ 864 if (traceData) { 865 traceData->setAddr(vaddr); 866 } 867 868 reqMade = true; 869 Request *req = new Request(); 870 req->setVirt(asid, vaddr, size, flags, PC); | 420 /** Returns the fault type. */ 421 Fault getFault() { return fault; } 422 423 /** Checks whether or not this instruction has had its branch target 424 * calculated yet. For now it is not utilized and is hacked to be 425 * always false. 426 * @todo: Actually use this instruction. 427 */ --- 438 unchanged lines hidden (view full) --- 866{ 867 if (traceData) { 868 traceData->setAddr(vaddr); 869 } 870 871 reqMade = true; 872 Request *req = new Request(); 873 req->setVirt(asid, vaddr, size, flags, PC); |
871 req->setThreadContext(thread->cpuId(), threadNumber); | 874 req->setThreadContext(thread->contextId(), threadNumber); |
872 873 fault = cpu->translateDataReadReq(req, thread); 874 875 if (fault == NoFault) 876 paddr = req->getPaddr(); 877 878 delete req; 879 return fault; 880} 881 882template<class Impl> 883template<class T> 884inline Fault 885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 886{ 887 reqMade = true; 888 Request *req = new Request(); 889 req->setVirt(asid, addr, sizeof(T), flags, this->PC); | 875 876 fault = cpu->translateDataReadReq(req, thread); 877 878 if (fault == NoFault) 879 paddr = req->getPaddr(); 880 881 delete req; 882 return fault; 883} 884 885template<class Impl> 886template<class T> 887inline Fault 888BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 889{ 890 reqMade = true; 891 Request *req = new Request(); 892 req->setVirt(asid, addr, sizeof(T), flags, this->PC); |
890 req->setThreadContext(thread->cpuId(), threadNumber); | 893 req->setThreadContext(thread->contextId(), threadNumber); |
891 892 fault = cpu->translateDataReadReq(req, thread); 893 894 if (req->isUncacheable()) 895 isUncacheable = true; 896 897 if (fault == NoFault) { 898 effAddr = req->getVaddr(); --- 38 unchanged lines hidden (view full) --- 937{ 938 if (traceData) { 939 traceData->setAddr(vaddr); 940 } 941 942 reqMade = true; 943 Request *req = new Request(); 944 req->setVirt(asid, vaddr, size, flags, PC); | 894 895 fault = cpu->translateDataReadReq(req, thread); 896 897 if (req->isUncacheable()) 898 isUncacheable = true; 899 900 if (fault == NoFault) { 901 effAddr = req->getVaddr(); --- 38 unchanged lines hidden (view full) --- 940{ 941 if (traceData) { 942 traceData->setAddr(vaddr); 943 } 944 945 reqMade = true; 946 Request *req = new Request(); 947 req->setVirt(asid, vaddr, size, flags, PC); |
945 req->setThreadContext(thread->cpuId(), threadNumber); | 948 req->setThreadContext(thread->contextId(), threadNumber); |
946 947 fault = cpu->translateDataWriteReq(req, thread); 948 949 if (fault == NoFault) 950 paddr = req->getPaddr(); 951 952 delete req; 953 return fault; --- 7 unchanged lines hidden (view full) --- 961 if (traceData) { 962 traceData->setAddr(addr); 963 traceData->setData(data); 964 } 965 966 reqMade = true; 967 Request *req = new Request(); 968 req->setVirt(asid, addr, sizeof(T), flags, this->PC); | 949 950 fault = cpu->translateDataWriteReq(req, thread); 951 952 if (fault == NoFault) 953 paddr = req->getPaddr(); 954 955 delete req; 956 return fault; --- 7 unchanged lines hidden (view full) --- 964 if (traceData) { 965 traceData->setAddr(addr); 966 traceData->setData(data); 967 } 968 969 reqMade = true; 970 Request *req = new Request(); 971 req->setVirt(asid, addr, sizeof(T), flags, this->PC); |
969 req->setThreadContext(thread->cpuId(), threadNumber); | 972 req->setThreadContext(thread->contextId(), threadNumber); |
970 971 fault = cpu->translateDataWriteReq(req, thread); 972 973 if (req->isUncacheable()) 974 isUncacheable = true; 975 976 if (fault == NoFault) { 977 effAddr = req->getVaddr(); --- 25 unchanged lines hidden --- | 973 974 fault = cpu->translateDataWriteReq(req, thread); 975 976 if (req->isUncacheable()) 977 isUncacheable = true; 978 979 if (fault == NoFault) { 980 effAddr = req->getVaddr(); --- 25 unchanged lines hidden --- |