base_dyn_inst.hh (5543:3af77710f397) base_dyn_inst.hh (5712:199d31b47f7b)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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407 public:
408 /** Dumps out contents of this BaseDynInst. */
409 void dump();
410
411 /** Dumps out contents of this BaseDynInst into given string. */
412 void dump(std::string &outstring);
413
414 /** Read this CPU's ID. */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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407 public:
408 /** Dumps out contents of this BaseDynInst. */
409 void dump();
410
411 /** Dumps out contents of this BaseDynInst into given string. */
412 void dump(std::string &outstring);
413
414 /** Read this CPU's ID. */
415 int readCpuId() { return cpu->readCpuId(); }
415 int cpuId() { return cpu->cpuId(); }
416
417 /** Returns the fault type. */
418 Fault getFault() { return fault; }
419
420 /** Checks whether or not this instruction has had its branch target
421 * calculated yet. For now it is not utilized and is hacked to be
422 * always false.
423 * @todo: Actually use this instruction.

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863{
864 if (traceData) {
865 traceData->setAddr(vaddr);
866 }
867
868 reqMade = true;
869 Request *req = new Request();
870 req->setVirt(asid, vaddr, size, flags, PC);
416
417 /** Returns the fault type. */
418 Fault getFault() { return fault; }
419
420 /** Checks whether or not this instruction has had its branch target
421 * calculated yet. For now it is not utilized and is hacked to be
422 * always false.
423 * @todo: Actually use this instruction.

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863{
864 if (traceData) {
865 traceData->setAddr(vaddr);
866 }
867
868 reqMade = true;
869 Request *req = new Request();
870 req->setVirt(asid, vaddr, size, flags, PC);
871 req->setThreadContext(thread->readCpuId(), threadNumber);
871 req->setThreadContext(thread->cpuId(), threadNumber);
872
873 fault = cpu->translateDataReadReq(req, thread);
874
875 if (fault == NoFault)
876 paddr = req->getPaddr();
877
878 delete req;
879 return fault;
880}
881
882template<class Impl>
883template<class T>
884inline Fault
885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
886{
887 reqMade = true;
888 Request *req = new Request();
889 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
872
873 fault = cpu->translateDataReadReq(req, thread);
874
875 if (fault == NoFault)
876 paddr = req->getPaddr();
877
878 delete req;
879 return fault;
880}
881
882template<class Impl>
883template<class T>
884inline Fault
885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
886{
887 reqMade = true;
888 Request *req = new Request();
889 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
890 req->setThreadContext(thread->readCpuId(), threadNumber);
890 req->setThreadContext(thread->cpuId(), threadNumber);
891
892 fault = cpu->translateDataReadReq(req, thread);
893
894 if (req->isUncacheable())
895 isUncacheable = true;
896
897 if (fault == NoFault) {
898 effAddr = req->getVaddr();

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937{
938 if (traceData) {
939 traceData->setAddr(vaddr);
940 }
941
942 reqMade = true;
943 Request *req = new Request();
944 req->setVirt(asid, vaddr, size, flags, PC);
891
892 fault = cpu->translateDataReadReq(req, thread);
893
894 if (req->isUncacheable())
895 isUncacheable = true;
896
897 if (fault == NoFault) {
898 effAddr = req->getVaddr();

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937{
938 if (traceData) {
939 traceData->setAddr(vaddr);
940 }
941
942 reqMade = true;
943 Request *req = new Request();
944 req->setVirt(asid, vaddr, size, flags, PC);
945 req->setThreadContext(thread->readCpuId(), threadNumber);
945 req->setThreadContext(thread->cpuId(), threadNumber);
946
947 fault = cpu->translateDataWriteReq(req, thread);
948
949 if (fault == NoFault)
950 paddr = req->getPaddr();
951
952 delete req;
953 return fault;

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961 if (traceData) {
962 traceData->setAddr(addr);
963 traceData->setData(data);
964 }
965
966 reqMade = true;
967 Request *req = new Request();
968 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
946
947 fault = cpu->translateDataWriteReq(req, thread);
948
949 if (fault == NoFault)
950 paddr = req->getPaddr();
951
952 delete req;
953 return fault;

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961 if (traceData) {
962 traceData->setAddr(addr);
963 traceData->setData(data);
964 }
965
966 reqMade = true;
967 Request *req = new Request();
968 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
969 req->setThreadContext(thread->readCpuId(), threadNumber);
969 req->setThreadContext(thread->cpuId(), threadNumber);
970
971 fault = cpu->translateDataWriteReq(req, thread);
972
973 if (req->isUncacheable())
974 isUncacheable = true;
975
976 if (fault == NoFault) {
977 effAddr = req->getVaddr();

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971 fault = cpu->translateDataWriteReq(req, thread);
972
973 if (req->isUncacheable())
974 isUncacheable = true;
975
976 if (fault == NoFault) {
977 effAddr = req->getVaddr();

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