base_dyn_inst.hh (3791:f1783bae1afe) base_dyn_inst.hh (3794:647d6bb9539a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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216 Addr nextPC;
217
218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
219 Addr nextNPC;
220
221 /** Predicted next PC. */
222 Addr predPC;
223
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 207 unchanged lines hidden (view full) ---

216 Addr nextPC;
217
218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
219 Addr nextNPC;
220
221 /** Predicted next PC. */
222 Addr predPC;
223
224 /** Predicted next NPC. */
225 Addr predNPC;
226
227 /** If this is a branch that was predicted taken */
228 bool predTaken;
229
224 /** Count of total number of dynamic instructions. */
225 static int instcount;
226
227#ifdef DEBUG
228 void dumpSNList();
229#endif
230
231 /** Whether or not the source register is ready.

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331 {
332 _flatDestRegIdx[idx] = flattened_dest;
333 }
334
335 /** BaseDynInst constructor given a binary instruction.
336 * @param inst The binary instruction.
337 * @param PC The PC of the instruction.
338 * @param pred_PC The predicted next PC.
230 /** Count of total number of dynamic instructions. */
231 static int instcount;
232
233#ifdef DEBUG
234 void dumpSNList();
235#endif
236
237 /** Whether or not the source register is ready.

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337 {
338 _flatDestRegIdx[idx] = flattened_dest;
339 }
340
341 /** BaseDynInst constructor given a binary instruction.
342 * @param inst The binary instruction.
343 * @param PC The PC of the instruction.
344 * @param pred_PC The predicted next PC.
345 * @param pred_NPC The predicted next NPC.
339 * @param seq_num The sequence number of the instruction.
340 * @param cpu Pointer to the instruction's CPU.
341 */
346 * @param seq_num The sequence number of the instruction.
347 * @param cpu Pointer to the instruction's CPU.
348 */
342 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC,
349 BaseDynInst(TheISA::ExtMachInst inst, Addr PC,
350 Addr pred_PC, Addr pred_NPC,
343 InstSeqNum seq_num, ImplCPU *cpu);
344
345 /** BaseDynInst constructor given a StaticInst pointer.
346 * @param _staticInst The StaticInst for this BaseDynInst.
347 */
348 BaseDynInst(StaticInstPtr &_staticInst);
349
350 /** BaseDynInst destructor. */

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380 Addr readNextPC() { return nextPC; }
381
382 /** Returns the next NPC. This could be the speculative next NPC if it is
383 * called prior to the actual branch target being calculated.
384 */
385 Addr readNextNPC() { return nextNPC; }
386
387 /** Set the predicted target of this current instruction. */
351 InstSeqNum seq_num, ImplCPU *cpu);
352
353 /** BaseDynInst constructor given a StaticInst pointer.
354 * @param _staticInst The StaticInst for this BaseDynInst.
355 */
356 BaseDynInst(StaticInstPtr &_staticInst);
357
358 /** BaseDynInst destructor. */

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388 Addr readNextPC() { return nextPC; }
389
390 /** Returns the next NPC. This could be the speculative next NPC if it is
391 * called prior to the actual branch target being calculated.
392 */
393 Addr readNextNPC() { return nextNPC; }
394
395 /** Set the predicted target of this current instruction. */
388 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
396 void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
397 {
398 predPC = predicted_PC;
399 predNPC = predicted_NPC;
400 }
389
401
390 /** Returns the predicted target of the branch. */
391 Addr readPredTarg() { return predPC; }
402 /** Returns the predicted PC immediately after the branch. */
403 Addr readPredPC() { return predPC; }
392
404
405 /** Returns the predicted PC two instructions after the branch */
406 Addr readPredNPC() { return predNPC; }
407
393 /** Returns whether the instruction was predicted taken or not. */
408 /** Returns whether the instruction was predicted taken or not. */
394 bool predTaken()
395#if ISA_HAS_DELAY_SLOT
396 { return predPC != (nextPC + sizeof(TheISA::MachInst)); }
397#else
398 { return predPC != (PC + sizeof(TheISA::MachInst)); }
399#endif
409 bool readPredTaken()
410 {
411 return predTaken;
412 }
400
413
414 void setPredTaken(bool predicted_taken)
415 {
416 predTaken = predicted_taken;
417 }
418
401 /** Returns whether the instruction mispredicted. */
402 bool mispredicted()
419 /** Returns whether the instruction mispredicted. */
420 bool mispredicted()
403#if ISA_HAS_DELAY_SLOT
404 { return predPC != nextNPC; }
405#else
406 { return predPC != nextPC; }
407#endif
421 {
422 return predPC != nextPC || predNPC != nextNPC;
423 }
424
408 //
409 // Instruction types. Forward checks to StaticInst object.
410 //
411 bool isNop() const { return staticInst->isNop(); }
412 bool isMemRef() const { return staticInst->isMemRef(); }
413 bool isLoad() const { return staticInst->isLoad(); }
414 bool isStore() const { return staticInst->isStore(); }
415 bool isStoreConditional() const

--- 434 unchanged lines hidden --- 		425 //
426 // Instruction types. Forward checks to StaticInst object.
427 //
428 bool isNop() const { return staticInst->isNop(); }
429 bool isMemRef() const { return staticInst->isMemRef(); }
430 bool isLoad() const { return staticInst->isLoad(); }
431 bool isStore() const { return staticInst->isStore(); }
432 bool isStoreConditional() const

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