base_dyn_inst.hh (3735:86a7cf4dcc11) base_dyn_inst.hh (3770:422aa205500a)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/o3/comm.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/inst_seq.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst.hh"
46#include "mem/packet.hh"
47#include "sim/system.hh"
48
49/**

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57template <class Impl>
58class BaseDynInst : public FastAlloc, public RefCounted
59{
60 public:
61 // Typedef for the CPU.
62 typedef typename Impl::CPUType ImplCPU;
63 typedef typename ImplCPU::ImplState ImplState;
64
43#include "cpu/exetrace.hh"
44#include "cpu/inst_seq.hh"
45#include "cpu/op_class.hh"
46#include "cpu/static_inst.hh"
47#include "mem/packet.hh"
48#include "sim/system.hh"
49
50/**

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58template <class Impl>
59class BaseDynInst : public FastAlloc, public RefCounted
60{
61 public:
62 // Typedef for the CPU.
63 typedef typename Impl::CPUType ImplCPU;
64 typedef typename ImplCPU::ImplState ImplState;
65
65 // Binary machine instruction type.
66 typedef TheISA::MachInst MachInst;
67 // Extended machine instruction type
68 typedef TheISA::ExtMachInst ExtMachInst;
69 // Logical register index type.
70 typedef TheISA::RegIndex RegIndex;
71 // Integer register type.
72 typedef TheISA::IntReg IntReg;
73 // Floating point register type.
74 typedef TheISA::FloatReg FloatReg;
75
76 // The DynInstPtr type.

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231 void dumpSNList();
232#endif
233
234 /** Whether or not the source register is ready.
235 * @todo: Not sure this should be here vs the derived class.
236 */
237 bool _readySrcRegIdx[MaxInstSrcRegs];
238
66 // Logical register index type.
67 typedef TheISA::RegIndex RegIndex;
68 // Integer register type.
69 typedef TheISA::IntReg IntReg;
70 // Floating point register type.
71 typedef TheISA::FloatReg FloatReg;
72
73 // The DynInstPtr type.

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228 void dumpSNList();
229#endif
230
231 /** Whether or not the source register is ready.
232 * @todo: Not sure this should be here vs the derived class.
233 */
234 bool _readySrcRegIdx[MaxInstSrcRegs];
235
236 protected:
237 /** Flattened register index of the destination registers of this
238 * instruction.
239 */
240 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
241
242 /** Flattened register index of the source registers of this
243 * instruction.
244 */
245 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
246
247 /** Physical register index of the destination registers of this
248 * instruction.
249 */
250 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
251
252 /** Physical register index of the source registers of this
253 * instruction.
254 */
255 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
256
257 /** Physical register index of the previous producers of the
258 * architected destinations.
259 */
260 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
261
239 public:
262 public:
263
264 /** Returns the physical register index of the i'th destination
265 * register.
266 */
267 PhysRegIndex renamedDestRegIdx(int idx) const
268 {
269 return _destRegIdx[idx];
270 }
271
272 /** Returns the physical register index of the i'th source register. */
273 PhysRegIndex renamedSrcRegIdx(int idx) const
274 {
275 return _srcRegIdx[idx];
276 }
277
278 /** Returns the flattened register index of the i'th destination
279 * register.
280 */
281 TheISA::RegIndex flattenedDestRegIdx(int idx) const
282 {
283 return _flatDestRegIdx[idx];
284 }
285
286 /** Returns the flattened register index of the i'th source register */
287 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
288 {
289 return _flatSrcRegIdx[idx];
290 }
291
292 /** Returns the physical register index of the previous physical register
293 * that remapped to the same logical register index.
294 */
295 PhysRegIndex prevDestRegIdx(int idx) const
296 {
297 return _prevDestRegIdx[idx];
298 }
299
300 /** Renames a destination register to a physical register. Also records
301 * the previous physical register that the logical register mapped to.
302 */
303 void renameDestReg(int idx,
304 PhysRegIndex renamed_dest,
305 PhysRegIndex previous_rename)
306 {
307 _destRegIdx[idx] = renamed_dest;
308 _prevDestRegIdx[idx] = previous_rename;
309 }
310
311 /** Renames a source logical register to the physical register which
312 * has/will produce that logical register's result.
313 * @todo: add in whether or not the source register is ready.
314 */
315 void renameSrcReg(int idx, PhysRegIndex renamed_src)
316 {
317 _srcRegIdx[idx] = renamed_src;
318 }
319
320 /** Flattens a source architectural register index into a logical index.
321 */
322 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
323 {
324 _flatSrcRegIdx[idx] = flattened_src;
325 }
326
327 /** Flattens a destination architectural register index into a logical
328 * index.
329 */
330 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
331 {
332 _flatDestRegIdx[idx] = flattened_dest;
333 }
334
240 /** BaseDynInst constructor given a binary instruction.
241 * @param inst The binary instruction.
242 * @param PC The PC of the instruction.
243 * @param pred_PC The predicted next PC.
244 * @param seq_num The sequence number of the instruction.
245 * @param cpu Pointer to the instruction's CPU.
246 */
335 /** BaseDynInst constructor given a binary instruction.
336 * @param inst The binary instruction.
337 * @param PC The PC of the instruction.
338 * @param pred_PC The predicted next PC.
339 * @param seq_num The sequence number of the instruction.
340 * @param cpu Pointer to the instruction's CPU.
341 */
247 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
248 ImplCPU *cpu);
342 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC,
343 InstSeqNum seq_num, ImplCPU *cpu);
249
250 /** BaseDynInst constructor given a StaticInst pointer.
251 * @param _staticInst The StaticInst for this BaseDynInst.
252 */
253 BaseDynInst(StaticInstPtr &_staticInst);
254
255 /** BaseDynInst destructor. */
256 ~BaseDynInst();

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293 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
294
295 /** Returns the predicted target of the branch. */
296 Addr readPredTarg() { return predPC; }
297
298 /** Returns whether the instruction was predicted taken or not. */
299 bool predTaken()
300#if ISA_HAS_DELAY_SLOT
344
345 /** BaseDynInst constructor given a StaticInst pointer.
346 * @param _staticInst The StaticInst for this BaseDynInst.
347 */
348 BaseDynInst(StaticInstPtr &_staticInst);
349
350 /** BaseDynInst destructor. */
351 ~BaseDynInst();

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388 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
389
390 /** Returns the predicted target of the branch. */
391 Addr readPredTarg() { return predPC; }
392
393 /** Returns whether the instruction was predicted taken or not. */
394 bool predTaken()
395#if ISA_HAS_DELAY_SLOT
301 { return predPC != (nextPC + sizeof(MachInst)); }
396 { return predPC != (nextPC + sizeof(TheISA::MachInst)); }
302#else
397#else
303 { return predPC != (PC + sizeof(MachInst)); }
398 { return predPC != (PC + sizeof(TheISA::MachInst)); }
304#endif
305
306 /** Returns whether the instruction mispredicted. */
307 bool mispredicted()
308#if ISA_HAS_DELAY_SLOT
309 { return predPC != nextNPC; }
310#else
311 { return predPC != nextPC; }

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401
402 /** Returns the result of a floating point instruction. */
403 float readFloatResult() { return (float)instResult.dbl; }
404
405 /** Returns the result of a floating point (double) instruction. */
406 double readDoubleResult() { return instResult.dbl; }
407
408 /** Records an integer register being set to a value. */
399#endif
400
401 /** Returns whether the instruction mispredicted. */
402 bool mispredicted()
403#if ISA_HAS_DELAY_SLOT
404 { return predPC != nextNPC; }
405#else
406 { return predPC != nextPC; }

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496
497 /** Returns the result of a floating point instruction. */
498 float readFloatResult() { return (float)instResult.dbl; }
499
500 /** Returns the result of a floating point (double) instruction. */
501 double readDoubleResult() { return instResult.dbl; }
502
503 /** Records an integer register being set to a value. */
409 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
504 void setIntReg(const StaticInst *si, int idx, uint64_t val)
410 {
411 if (recordResult)
412 instResult.integer = val;
413 }
414
415 /** Records an fp register being set to a value. */
505 {
506 if (recordResult)
507 instResult.integer = val;
508 }
509
510 /** Records an fp register being set to a value. */
416 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
417 int width)
511 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
418 {
419 if (recordResult) {
420 if (width == 32)
421 instResult.dbl = (double)val;
422 else if (width == 64)
423 instResult.dbl = val;
424 else
425 panic("Unsupported width!");
426 }
427 }
428
429 /** Records an fp register being set to a value. */
512 {
513 if (recordResult) {
514 if (width == 32)
515 instResult.dbl = (double)val;
516 else if (width == 64)
517 instResult.dbl = val;
518 else
519 panic("Unsupported width!");
520 }
521 }
522
523 /** Records an fp register being set to a value. */
430 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
524 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
431 {
432 if (recordResult)
433 instResult.dbl = (double)val;
434 }
435
436 /** Records an fp register being set to an integer value. */
525 {
526 if (recordResult)
527 instResult.dbl = (double)val;
528 }
529
530 /** Records an fp register being set to an integer value. */
437 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
438 int width)
531 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
439 {
440 if (recordResult)
441 instResult.integer = val;
442 }
443
444 /** Records an fp register being set to an integer value. */
532 {
533 if (recordResult)
534 instResult.integer = val;
535 }
536
537 /** Records an fp register being set to an integer value. */
445 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
538 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
446 {
447 if (recordResult)
448 instResult.integer = val;
449 }
450
451 /** Records that one of the source registers is ready. */
452 void markSrcRegReady();
453

--- 301 unchanged lines hidden --- 		539 {
540 if (recordResult)
541 instResult.integer = val;
542 }
543
544 /** Records that one of the source registers is ready. */
545 void markSrcRegReady();
546

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