base_dyn_inst.hh (2733:e0eac8fc5774) base_dyn_inst.hh (2935:d1223a6c9156)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 201 unchanged lines hidden (view full) ---

210 Addr PC;
211
212 /** Next non-speculative PC. It is not filled in at fetch, but rather
213 * once the target of the branch is truly known (either decode or
214 * execute).
215 */
216 Addr nextPC;
217
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 201 unchanged lines hidden (view full) ---

210 Addr PC;
211
212 /** Next non-speculative PC. It is not filled in at fetch, but rather
213 * once the target of the branch is truly known (either decode or
214 * execute).
215 */
216 Addr nextPC;
217
218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
219 Addr nextNPC;
220
218 /** Predicted next PC. */
219 Addr predPC;
220
221 /** Count of total number of dynamic instructions. */
222 static int instcount;
223
224#ifdef DEBUG
225 void dumpSNList();

--- 44 unchanged lines hidden (view full) ---

270 */
271 bool doneTargCalc() { return false; }
272
273 /** Returns the next PC. This could be the speculative next PC if it is
274 * called prior to the actual branch target being calculated.
275 */
276 Addr readNextPC() { return nextPC; }
277
221 /** Predicted next PC. */
222 Addr predPC;
223
224 /** Count of total number of dynamic instructions. */
225 static int instcount;
226
227#ifdef DEBUG
228 void dumpSNList();

--- 44 unchanged lines hidden (view full) ---

273 */
274 bool doneTargCalc() { return false; }
275
276 /** Returns the next PC. This could be the speculative next PC if it is
277 * called prior to the actual branch target being calculated.
278 */
279 Addr readNextPC() { return nextPC; }
280
281 /** Returns the next NPC. This could be the speculative next NPC if it is
282 * called prior to the actual branch target being calculated.
283 */
284 Addr readNextNPC() { return nextNPC; }
285
278 /** Set the predicted target of this current instruction. */
279 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
280
281 /** Returns the predicted target of the branch. */
282 Addr readPredTarg() { return predPC; }
283
284 /** Returns whether the instruction was predicted taken or not. */
286 /** Set the predicted target of this current instruction. */
287 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
288
289 /** Returns the predicted target of the branch. */
290 Addr readPredTarg() { return predPC; }
291
292 /** Returns whether the instruction was predicted taken or not. */
285 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
293 bool predTaken()
294#if THE_ISA == ALPHA_ISA
295 { return predPC != (PC + sizeof(MachInst)); }
296#else
297 { return predPC != (nextPC + sizeof(MachInst)); }
298#endif
286
287 /** Returns whether the instruction mispredicted. */
299
300 /** Returns whether the instruction mispredicted. */
288 bool mispredicted() { return predPC != nextPC; }
289
301 bool mispredicted()
302#if THE_ISA == ALPHA_ISA
303 { return predPC != nextPC; }
304#else
305 { return predPC != nextNPC; }
306#endif
290 //
291 // Instruction types. Forward checks to StaticInst object.
292 //
293 bool isNop() const { return staticInst->isNop(); }
294 bool isMemRef() const { return staticInst->isMemRef(); }
295 bool isLoad() const { return staticInst->isLoad(); }
296 bool isStore() const { return staticInst->isStore(); }
297 bool isStoreConditional() const

--- 5 unchanged lines hidden (view full) ---

303 bool isFloating() const { return staticInst->isFloating(); }
304 bool isControl() const { return staticInst->isControl(); }
305 bool isCall() const { return staticInst->isCall(); }
306 bool isReturn() const { return staticInst->isReturn(); }
307 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
308 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
309 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
310 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
307 //
308 // Instruction types. Forward checks to StaticInst object.
309 //
310 bool isNop() const { return staticInst->isNop(); }
311 bool isMemRef() const { return staticInst->isMemRef(); }
312 bool isLoad() const { return staticInst->isLoad(); }
313 bool isStore() const { return staticInst->isStore(); }
314 bool isStoreConditional() const

--- 5 unchanged lines hidden (view full) ---

320 bool isFloating() const { return staticInst->isFloating(); }
321 bool isControl() const { return staticInst->isControl(); }
322 bool isCall() const { return staticInst->isCall(); }
323 bool isReturn() const { return staticInst->isReturn(); }
324 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
325 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
326 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
327 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
328 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
311 bool isThreadSync() const { return staticInst->isThreadSync(); }
312 bool isSerializing() const { return staticInst->isSerializing(); }
313 bool isSerializeBefore() const
314 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
315 bool isSerializeAfter() const
316 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
317 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
318 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }

--- 221 unchanged lines hidden (view full) ---

540 const Addr readPC() const { return PC; }
541
542 /** Set the next PC of this instruction (its actual target). */
543 void setNextPC(uint64_t val)
544 {
545 nextPC = val;
546 }
547
329 bool isThreadSync() const { return staticInst->isThreadSync(); }
330 bool isSerializing() const { return staticInst->isSerializing(); }
331 bool isSerializeBefore() const
332 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
333 bool isSerializeAfter() const
334 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
335 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
336 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }

--- 221 unchanged lines hidden (view full) ---

558 const Addr readPC() const { return PC; }
559
560 /** Set the next PC of this instruction (its actual target). */
561 void setNextPC(uint64_t val)
562 {
563 nextPC = val;
564 }
565
566 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
567 void setNextNPC(uint64_t val)
568 {
569 nextNPC = val;
570 }
571
548 /** Sets the ASID. */
549 void setASID(short addr_space_id) { asid = addr_space_id; }
550
551 /** Sets the thread id. */
552 void setTid(unsigned tid) { threadNumber = tid; }
553
554 /** Sets the pointer to the thread state. */
555 void setThreadState(ImplState *state) { thread = state; }

--- 152 unchanged lines hidden --- 		572 /** Sets the ASID. */
573 void setASID(short addr_space_id) { asid = addr_space_id; }
574
575 /** Sets the thread id. */
576 void setTid(unsigned tid) { threadNumber = tid; }
577
578 /** Sets the pointer to the thread state. */
579 void setThreadState(ImplState *state) { thread = state; }

--- 152 unchanged lines hidden ---