base_dyn_inst.hh (2702:8a3ee279559b) base_dyn_inst.hh (2731:822b96578fba)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <bitset>
34#include <list>
35#include <string>
36
37#include "arch/faults.hh"
38#include "base/fast_alloc.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "cpu/exetrace.hh"

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121 Fault copySrcTranslate(Addr src);
122 Fault copy(Addr dest);
123
124 /** @todo: Consider making this private. */
125 public:
126 /** The sequence number of the instruction. */
127 InstSeqNum seqNum;
128
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/exetrace.hh"

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122 Fault copySrcTranslate(Addr src);
123 Fault copy(Addr dest);
124
125 /** @todo: Consider making this private. */
126 public:
127 /** The sequence number of the instruction. */
128 InstSeqNum seqNum;
129
129 /** Is the instruction in the IQ */
130 bool iqEntry;
130 enum Status {
131 IqEntry, /// Instruction is in the IQ
132 RobEntry, /// Instruction is in the ROB
133 LsqEntry, /// Instruction is in the LSQ
134 Completed, /// Instruction has completed
135 ResultReady, /// Instruction has its result
136 CanIssue, /// Instruction can issue and execute
137 Issued, /// Instruction has issued
138 Executed, /// Instruction has executed
139 CanCommit, /// Instruction can commit
140 AtCommit, /// Instruction has reached commit
141 Committed, /// Instruction has committed
142 Squashed, /// Instruction is squashed
143 SquashedInIQ, /// Instruction is squashed in the IQ
144 SquashedInLSQ, /// Instruction is squashed in the LSQ
145 SquashedInROB, /// Instruction is squashed in the ROB
146 RecoverInst, /// Is a recover instruction
147 BlockingInst, /// Is a blocking instruction
148 ThreadsyncWait, /// Is a thread synchronization instruction
149 SerializeBefore, /// Needs to serialize on
150 /// instructions ahead of it
151 SerializeAfter, /// Needs to serialize instructions behind it
152 SerializeHandled, /// Serialization has been handled
153 NumStatus
154 };
131
155
132 /** Is the instruction in the ROB */
133 bool robEntry;
156 /** The status of this BaseDynInst. Several bits can be set. */
157 std::bitset<NumStatus> status;
134
158
135 /** Is the instruction in the LSQ */
136 bool lsqEntry;
137
138 /** Is the instruction completed. */
139 bool completed;
140
141 /** Is the instruction's result ready. */
142 bool resultReady;
143
144 /** Can this instruction issue. */
145 bool canIssue;
146
147 /** Has this instruction issued. */
148 bool issued;
149
150 /** Has this instruction executed (or made it through execute) yet. */
151 bool executed;
152
153 /** Can this instruction commit. */
154 bool canCommit;
155
156 /** Is this instruction committed. */
157 bool committed;
158
159 /** Is this instruction squashed. */
160 bool squashed;
161
162 /** Is this instruction squashed in the instruction queue. */
163 bool squashedInIQ;
164
165 /** Is this instruction squashed in the instruction queue. */
166 bool squashedInLSQ;
167
168 /** Is this instruction squashed in the instruction queue. */
169 bool squashedInROB;
170
171 /** Is this a recover instruction. */
172 bool recoverInst;
173
174 /** Is this a thread blocking instruction. */
175 bool blockingInst; /* this inst has called thread_block() */
176
177 /** Is this a thread syncrhonization instruction. */
178 bool threadsyncWait;
179
180 /** The thread this instruction is from. */
181 short threadNumber;
182
183 /** data address space ID, for loads & stores. */
184 short asid;
185
186 /** How many source registers are ready. */
187 unsigned readyRegs;

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211 Addr copySrcEffAddr;
212
213 /** Effective physical address for a copy source. */
214 Addr copySrcPhysEffAddr;
215
216 /** The memory request flags (from translation). */
217 unsigned memReqFlags;
218
159 /** The thread this instruction is from. */
160 short threadNumber;
161
162 /** data address space ID, for loads & stores. */
163 short asid;
164
165 /** How many source registers are ready. */
166 unsigned readyRegs;

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190 Addr copySrcEffAddr;
191
192 /** Effective physical address for a copy source. */
193 Addr copySrcPhysEffAddr;
194
195 /** The memory request flags (from translation). */
196 unsigned memReqFlags;
197
219 /** The size of the data to be stored. */
220 int storeSize;
221
222 /** The data to be stored. */
223 IntReg storeData;
224
225 union Result {
226 uint64_t integer;
227 float fp;
228 double dbl;
229 };
230
231 /** The result of the instruction; assumes for now that there's only one
232 * destination register.

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333 bool isReturn() const { return staticInst->isReturn(); }
334 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
335 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
336 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
337 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
338 bool isThreadSync() const { return staticInst->isThreadSync(); }
339 bool isSerializing() const { return staticInst->isSerializing(); }
340 bool isSerializeBefore() const
198 union Result {
199 uint64_t integer;
200 float fp;
201 double dbl;
202 };
203
204 /** The result of the instruction; assumes for now that there's only one
205 * destination register.

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306 bool isReturn() const { return staticInst->isReturn(); }
307 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
308 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
309 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
310 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
311 bool isThreadSync() const { return staticInst->isThreadSync(); }
312 bool isSerializing() const { return staticInst->isSerializing(); }
313 bool isSerializeBefore() const
341 { return staticInst->isSerializeBefore() || serializeBefore; }
314 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
342 bool isSerializeAfter() const
315 bool isSerializeAfter() const
343 { return staticInst->isSerializeAfter() || serializeAfter; }
316 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
344 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
345 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
346 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
347 bool isQuiesce() const { return staticInst->isQuiesce(); }
348 bool isIprAccess() const { return staticInst->isIprAccess(); }
349 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
350
351 /** Temporarily sets this instruction as a serialize before instruction. */
317 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
318 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
319 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
320 bool isQuiesce() const { return staticInst->isQuiesce(); }
321 bool isIprAccess() const { return staticInst->isIprAccess(); }
322 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
323
324 /** Temporarily sets this instruction as a serialize before instruction. */
352 void setSerializeBefore() { serializeBefore = true; }
325 void setSerializeBefore() { status.set(SerializeBefore); }
353
354 /** Clears the serializeBefore part of this instruction. */
326
327 /** Clears the serializeBefore part of this instruction. */
355 void clearSerializeBefore() { serializeBefore = false; }
328 void clearSerializeBefore() { status.reset(SerializeBefore); }
356
357 /** Checks if this serializeBefore is only temporarily set. */
329
330 /** Checks if this serializeBefore is only temporarily set. */
358 bool isTempSerializeBefore() { return serializeBefore; }
331 bool isTempSerializeBefore() { return status[SerializeBefore]; }
359
332
360 /** Tracks if instruction has been externally set as serializeBefore. */
361 bool serializeBefore;
362
363 /** Temporarily sets this instruction as a serialize after instruction. */
333 /** Temporarily sets this instruction as a serialize after instruction. */
364 void setSerializeAfter() { serializeAfter = true; }
334 void setSerializeAfter() { status.set(SerializeAfter); }
365
366 /** Clears the serializeAfter part of this instruction.*/
335
336 /** Clears the serializeAfter part of this instruction.*/
367 void clearSerializeAfter() { serializeAfter = false; }
337 void clearSerializeAfter() { status.reset(SerializeAfter); }
368
369 /** Checks if this serializeAfter is only temporarily set. */
338
339 /** Checks if this serializeAfter is only temporarily set. */
370 bool isTempSerializeAfter() { return serializeAfter; }
340 bool isTempSerializeAfter() { return status[SerializeAfter]; }
371
341
372 /** Tracks if instruction has been externally set as serializeAfter. */
373 bool serializeAfter;
342 /** Sets the serialization part of this instruction as handled. */
343 void setSerializeHandled() { status.set(SerializeHandled); }
374
375 /** Checks if the serialization part of this instruction has been
376 * handled. This does not apply to the temporary serializing
377 * state; it only applies to this instruction's own permanent
378 * serializing state.
379 */
344
345 /** Checks if the serialization part of this instruction has been
346 * handled. This does not apply to the temporary serializing
347 * state; it only applies to this instruction's own permanent
348 * serializing state.
349 */
380 bool isSerializeHandled() { return serializeHandled; }
350 bool isSerializeHandled() { return status[SerializeHandled]; }
381
351
382 /** Sets the serialization part of this instruction as handled. */
383 void setSerializeHandled() { serializeHandled = true; }
384
385 /** Whether or not the serialization of this instruction has been handled. */
386 bool serializeHandled;
387
388 /** Returns the opclass of this instruction. */
389 OpClass opClass() const { return staticInst->opClass(); }
390
391 /** Returns the branch target address. */
392 Addr branchTarget() const { return staticInst->branchTarget(PC); }
393
394 /** Returns the number of source registers. */
395 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }

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460
461 /** Returns if a source register is ready. */
462 bool isReadySrcRegIdx(int idx) const
463 {
464 return this->_readySrcRegIdx[idx];
465 }
466
467 /** Sets this instruction as completed. */
352 /** Returns the opclass of this instruction. */
353 OpClass opClass() const { return staticInst->opClass(); }
354
355 /** Returns the branch target address. */
356 Addr branchTarget() const { return staticInst->branchTarget(PC); }
357
358 /** Returns the number of source registers. */
359 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }

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424
425 /** Returns if a source register is ready. */
426 bool isReadySrcRegIdx(int idx) const
427 {
428 return this->_readySrcRegIdx[idx];
429 }
430
431 /** Sets this instruction as completed. */
468 void setCompleted() { completed = true; }
432 void setCompleted() { status.set(Completed); }
469
470 /** Returns whether or not this instruction is completed. */
433
434 /** Returns whether or not this instruction is completed. */
471 bool isCompleted() const { return completed; }
435 bool isCompleted() const { return status[Completed]; }
472
436
473 void setResultReady() { resultReady = true; }
437 /** Marks the result as ready. */
438 void setResultReady() { status.set(ResultReady); }
474
439
475 bool isResultReady() const { return resultReady; }
440 /** Returns whether or not the result is ready. */
441 bool isResultReady() const { return status[ResultReady]; }
476
477 /** Sets this instruction as ready to issue. */
442
443 /** Sets this instruction as ready to issue. */
478 void setCanIssue() { canIssue = true; }
444 void setCanIssue() { status.set(CanIssue); }
479
480 /** Returns whether or not this instruction is ready to issue. */
445
446 /** Returns whether or not this instruction is ready to issue. */
481 bool readyToIssue() const { return canIssue; }
447 bool readyToIssue() const { return status[CanIssue]; }
482
483 /** Sets this instruction as issued from the IQ. */
448
449 /** Sets this instruction as issued from the IQ. */
484 void setIssued() { issued = true; }
450 void setIssued() { status.set(Issued); }
485
486 /** Returns whether or not this instruction has issued. */
451
452 /** Returns whether or not this instruction has issued. */
487 bool isIssued() const { return issued; }
453 bool isIssued() const { return status[Issued]; }
488
489 /** Sets this instruction as executed. */
454
455 /** Sets this instruction as executed. */
490 void setExecuted() { executed = true; }
456 void setExecuted() { status.set(Executed); }
491
492 /** Returns whether or not this instruction has executed. */
457
458 /** Returns whether or not this instruction has executed. */
493 bool isExecuted() const { return executed; }
459 bool isExecuted() const { return status[Executed]; }
494
495 /** Sets this instruction as ready to commit. */
460
461 /** Sets this instruction as ready to commit. */
496 void setCanCommit() { canCommit = true; }
462 void setCanCommit() { status.set(CanCommit); }
497
498 /** Clears this instruction as being ready to commit. */
463
464 /** Clears this instruction as being ready to commit. */
499 void clearCanCommit() { canCommit = false; }
465 void clearCanCommit() { status.reset(CanCommit); }
500
501 /** Returns whether or not this instruction is ready to commit. */
466
467 /** Returns whether or not this instruction is ready to commit. */
502 bool readyToCommit() const { return canCommit; }
468 bool readyToCommit() const { return status[CanCommit]; }
503
469
470 void setAtCommit() { status.set(AtCommit); }
471
472 bool isAtCommit() { return status[AtCommit]; }
473
504 /** Sets this instruction as committed. */
474 /** Sets this instruction as committed. */
505 void setCommitted() { committed = true; }
475 void setCommitted() { status.set(Committed); }
506
507 /** Returns whether or not this instruction is committed. */
476
477 /** Returns whether or not this instruction is committed. */
508 bool isCommitted() const { return committed; }
478 bool isCommitted() const { return status[Committed]; }
509
510 /** Sets this instruction as squashed. */
479
480 /** Sets this instruction as squashed. */
511 void setSquashed() { squashed = true; }
481 void setSquashed() { status.set(Squashed); }
512
513 /** Returns whether or not this instruction is squashed. */
482
483 /** Returns whether or not this instruction is squashed. */
514 bool isSquashed() const { return squashed; }
484 bool isSquashed() const { return status[Squashed]; }
515
516 //Instruction Queue Entry
517 //-----------------------
518 /** Sets this instruction as a entry the IQ. */
485
486 //Instruction Queue Entry
487 //-----------------------
488 /** Sets this instruction as a entry the IQ. */
519 void setInIQ() { iqEntry = true; }
489 void setInIQ() { status.set(IqEntry); }
520
521 /** Sets this instruction as a entry the IQ. */
490
491 /** Sets this instruction as a entry the IQ. */
522 void removeInIQ() { iqEntry = false; }
492 void clearInIQ() { status.reset(IqEntry); }
523
493
494 /** Returns whether or not this instruction has issued. */
495 bool isInIQ() const { return status[IqEntry]; }
496
524 /** Sets this instruction as squashed in the IQ. */
497 /** Sets this instruction as squashed in the IQ. */
525 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
498 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
526
527 /** Returns whether or not this instruction is squashed in the IQ. */
499
500 /** Returns whether or not this instruction is squashed in the IQ. */
528 bool isSquashedInIQ() const { return squashedInIQ; }
501 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
529
502
530 /** Returns whether or not this instruction has issued. */
531 bool isInIQ() const { return iqEntry; }
532
503
533
534 //Load / Store Queue Functions
535 //-----------------------
536 /** Sets this instruction as a entry the LSQ. */
504 //Load / Store Queue Functions
505 //-----------------------
506 /** Sets this instruction as a entry the LSQ. */
537 void setInLSQ() { lsqEntry = true; }
507 void setInLSQ() { status.set(LsqEntry); }
538
539 /** Sets this instruction as a entry the LSQ. */
508
509 /** Sets this instruction as a entry the LSQ. */
540 void removeInLSQ() { lsqEntry = false; }
510 void removeInLSQ() { status.reset(LsqEntry); }
541
511
512 /** Returns whether or not this instruction is in the LSQ. */
513 bool isInLSQ() const { return status[LsqEntry]; }
514
542 /** Sets this instruction as squashed in the LSQ. */
515 /** Sets this instruction as squashed in the LSQ. */
543 void setSquashedInLSQ() { squashedInLSQ = true;}
516 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
544
545 /** Returns whether or not this instruction is squashed in the LSQ. */
517
518 /** Returns whether or not this instruction is squashed in the LSQ. */
546 bool isSquashedInLSQ() const { return squashedInLSQ; }
519 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
547
520
548 /** Returns whether or not this instruction is in the LSQ. */
549 bool isInLSQ() const { return lsqEntry; }
550
521
551
552 //Reorder Buffer Functions
553 //-----------------------
554 /** Sets this instruction as a entry the ROB. */
522 //Reorder Buffer Functions
523 //-----------------------
524 /** Sets this instruction as a entry the ROB. */
555 void setInROB() { robEntry = true; }
525 void setInROB() { status.set(RobEntry); }
556
557 /** Sets this instruction as a entry the ROB. */
526
527 /** Sets this instruction as a entry the ROB. */
558 void removeInROB() { robEntry = false; }
528 void clearInROB() { status.reset(RobEntry); }
559
529
530 /** Returns whether or not this instruction is in the ROB. */
531 bool isInROB() const { return status[RobEntry]; }
532
560 /** Sets this instruction as squashed in the ROB. */
533 /** Sets this instruction as squashed in the ROB. */
561 void setSquashedInROB() { squashedInROB = true; }
534 void setSquashedInROB() { status.set(SquashedInROB); }
562
563 /** Returns whether or not this instruction is squashed in the ROB. */
535
536 /** Returns whether or not this instruction is squashed in the ROB. */
564 bool isSquashedInROB() const { return squashedInROB; }
537 bool isSquashedInROB() const { return status[SquashedInROB]; }
565
538
566 /** Returns whether or not this instruction is in the ROB. */
567 bool isInROB() const { return robEntry; }
568
569 /** Read the PC of this instruction. */
570 const Addr readPC() const { return PC; }
571
572 /** Set the next PC of this instruction (its actual target). */
573 void setNextPC(uint64_t val)
574 {
575 nextPC = val;
576 }
577
578 /** Sets the ASID. */
579 void setASID(short addr_space_id) { asid = addr_space_id; }
580
581 /** Sets the thread id. */
582 void setTid(unsigned tid) { threadNumber = tid; }
583
539 /** Read the PC of this instruction. */
540 const Addr readPC() const { return PC; }
541
542 /** Set the next PC of this instruction (its actual target). */
543 void setNextPC(uint64_t val)
544 {
545 nextPC = val;
546 }
547
548 /** Sets the ASID. */
549 void setASID(short addr_space_id) { asid = addr_space_id; }
550
551 /** Sets the thread id. */
552 void setTid(unsigned tid) { threadNumber = tid; }
553
554 /** Sets the pointer to the thread state. */
584 void setThreadState(ImplState *state) { thread = state; }
585
555 void setThreadState(ImplState *state) { thread = state; }
556
586 /** Returns the thread context.
587 */
557 /** Returns the thread context. */
588 ThreadContext *tcBase() { return thread->getTC(); }
589
590 private:
591 /** Instruction effective address.
592 * @todo: Consider if this is necessary or not.
593 */
594 Addr instEffAddr;
595

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616
617 public:
618 /** Load queue index. */
619 int16_t lqIdx;
620
621 /** Store queue index. */
622 int16_t sqIdx;
623
558 ThreadContext *tcBase() { return thread->getTC(); }
559
560 private:
561 /** Instruction effective address.
562 * @todo: Consider if this is necessary or not.
563 */
564 Addr instEffAddr;
565

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586
587 public:
588 /** Load queue index. */
589 int16_t lqIdx;
590
591 /** Store queue index. */
592 int16_t sqIdx;
593
624 bool reachedCommit;
625
626 /** Iterator pointing to this BaseDynInst in the list of all insts. */
627 ListIt instListIt;
628
629 /** Returns iterator to this instruction in the list of all insts. */
630 ListIt &getInstListIt() { return instListIt; }
631
632 /** Sets iterator for this instruction in the list of all insts. */
633 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

--- 106 unchanged lines hidden --- 		594 /** Iterator pointing to this BaseDynInst in the list of all insts. */
595 ListIt instListIt;
596
597 /** Returns iterator to this instruction in the list of all insts. */
598 ListIt &getInstListIt() { return instListIt; }
599
600 /** Sets iterator for this instruction in the list of all insts. */
601 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

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