base_dyn_inst.hh (2690:f4337c0d9e6f) base_dyn_inst.hh (2695:07d258482551)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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649 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
650};
651
652template<class Impl>
653template<class T>
654inline Fault
655BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
656{
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 640 unchanged lines hidden (view full) ---

649 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
650};
651
652template<class Impl>
653template<class T>
654inline Fault
655BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
656{
657 if (executed) {
658 panic("Not supposed to re-execute with split mem ops!");
659 fault = cpu->read(req, data, lqIdx);
660 return fault;
657 // Sometimes reads will get retried, so they may come through here
658 // twice.
659 if (!req) {
660 req = new Request();
661 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
662 req->setThreadContext(thread->readCpuId(), threadNumber);
663 } else {
664 assert(addr == req->getVaddr());
661 }
662
665 }
666
663 req = new Request();
664 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
665 req->setThreadContext(thread->readCpuId(), threadNumber);
666
667 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
668 TheISA::VMPageSize) {
669 return TheISA::genAlignmentFault();
670 }
671
672 fault = cpu->translateDataReadReq(req, thread);
673
674 if (fault == NoFault) {

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710inline Fault
711BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
712{
713 if (traceData) {
714 traceData->setAddr(addr);
715 traceData->setData(data);
716 }
717
667 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
668 TheISA::VMPageSize) {
669 return TheISA::genAlignmentFault();
670 }
671
672 fault = cpu->translateDataReadReq(req, thread);
673
674 if (fault == NoFault) {

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710inline Fault
711BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
712{
713 if (traceData) {
714 traceData->setAddr(addr);
715 traceData->setData(data);
716 }
717
718 assert(req == NULL);
719
718 req = new Request();
719 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
720 req->setThreadContext(thread->readCpuId(), threadNumber);
721
722 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
723 TheISA::VMPageSize) {
724 return TheISA::genAlignmentFault();
725 }

--- 28 unchanged lines hidden --- 		720 req = new Request();
721 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
722 req->setThreadContext(thread->readCpuId(), threadNumber);
723
724 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
725 TheISA::VMPageSize) {
726 return TheISA::genAlignmentFault();
727 }

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