base_dyn_inst.hh (13590:d7e018859709) | base_dyn_inst.hh (13610:5d5404ac6288) |
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1/* 2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 570 unchanged lines hidden (view full) --- 579 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 580 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 581 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 582 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 583 int8_t numVecElemDestRegs() const 584 { 585 return staticInst->numVecElemDestRegs(); 586 } | 1/* 2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 570 unchanged lines hidden (view full) --- 579 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 580 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 581 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 582 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 583 int8_t numVecElemDestRegs() const 584 { 585 return staticInst->numVecElemDestRegs(); 586 } |
587 int8_t 588 numVecPredDestRegs() const 589 { 590 return staticInst->numVecPredDestRegs(); 591 } |
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587 588 /** Returns the logical register index of the i'th destination register. */ 589 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 590 591 /** Returns the logical register index of the i'th source register. */ 592 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 593 594 /** Return the size of the instResult queue. */ --- 38 unchanged lines hidden (view full) --- 633 template<typename T> 634 void setVecElemResult(T&& t) 635 { 636 if (instFlags[RecordResult]) { 637 instResult.push(InstResult(std::forward<T>(t), 638 InstResult::ResultType::VecElem)); 639 } 640 } | 592 593 /** Returns the logical register index of the i'th destination register. */ 594 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 595 596 /** Returns the logical register index of the i'th source register. */ 597 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 598 599 /** Return the size of the instResult queue. */ --- 38 unchanged lines hidden (view full) --- 638 template<typename T> 639 void setVecElemResult(T&& t) 640 { 641 if (instFlags[RecordResult]) { 642 instResult.push(InstResult(std::forward<T>(t), 643 InstResult::ResultType::VecElem)); 644 } 645 } |
646 647 /** Predicate result. */ 648 template<typename T> 649 void setVecPredResult(T&& t) 650 { 651 if (instFlags[RecordResult]) { 652 instResult.push(InstResult(std::forward<T>(t), 653 InstResult::ResultType::VecPredReg)); 654 } 655 } |
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641 /** @} */ 642 643 /** Records an integer register being set to a value. */ 644 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 645 { 646 setScalarResult(val); 647 } 648 --- 18 unchanged lines hidden (view full) --- 667 } 668 669 /** Record a vector register being set to a value */ 670 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 671 { 672 setVecElemResult(val); 673 } 674 | 656 /** @} */ 657 658 /** Records an integer register being set to a value. */ 659 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 660 { 661 setScalarResult(val); 662 } 663 --- 18 unchanged lines hidden (view full) --- 682 } 683 684 /** Record a vector register being set to a value */ 685 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 686 { 687 setVecElemResult(val); 688 } 689 |
690 /** Record a vector register being set to a value */ 691 void setVecPredRegOperand(const StaticInst *si, int idx, 692 const VecPredRegContainer& val) 693 { 694 setVecPredResult(val); 695 } 696 |
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675 /** Records that one of the source registers is ready. */ 676 void markSrcRegReady(); 677 678 /** Marks a specific register as ready. */ 679 void markSrcRegReady(RegIndex src_idx); 680 681 /** Returns if a source register is ready. */ 682 bool isReadySrcRegIdx(int idx) const --- 219 unchanged lines hidden --- | 697 /** Records that one of the source registers is ready. */ 698 void markSrcRegReady(); 699 700 /** Marks a specific register as ready. */ 701 void markSrcRegReady(RegIndex src_idx); 702 703 /** Returns if a source register is ready. */ 704 bool isReadySrcRegIdx(int idx) const --- 219 unchanged lines hidden --- |